A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier
- 20 December 2017
- journal article
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 53 (4) , 1115-1126
Abstract
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.Keywords
Funding Information
- Broadcom
- Delft University of Technology, the Netherlands
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