Compact and High-Performing Five-Stage Pipeline RISC-V Microprocessor Designed for IoT Applications

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Abstract
This paper proposes a 32-bit five-stage pipelined microprocessor based on the RISC-V instruction set architecture to enhance pipeline execution efficiency. An enhanced Harvard architecture utilizing dual-port ROM is employed to facilitate parallel execution of instruction fetch and memory access operations. Additionally, a three-level address selector is designed to minimize pipeline flush processing cycles resulting from prediction failures. Furthermore, a data forward unit is implemented to mitigate the impact of data hazards on the pipeline, and a two-stage pipeline memory access structure is devised to eliminate pipeline stalls caused by memory access operations. The experimental results show that the processor designed in this paper can operate up to 110 MHz with a CoreMark score of 2.98. The CoreMark*Freq. of the proposed processor exceeds that of the Taiga processor by approximately 15%, and surpasses the VexRiscv processor by approximately 7%. The microprocessor presented in this paper features a compact footprint and high performance, making it highly applicable in the field of Internet of Things.
Funding Information
  • Natural Science Foundation of Hubei Province (2022CFB840)
  • National Natural Science Foundation of China (62201621)
  • Hubei Provincial Key Research Development Program Projects (2023BAB082)