Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology
Authors:
- 7 April 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 988-991
Abstract
3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performanceKeywords
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