Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices
Authors:
- K. KatsukiKKK. Katsuki
- M. KotaniMKM. Kotani
- K. KobayashiKKK. Kobayashi
- H. OnoderaHOH. Onodera
- 22 March 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 110-111
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A yield and speed enhancement scheme under within-die variations on 90nm LUT array2006
- The impact of device parameter variations on the frequency and performance of VLSI chips2005
- Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device Matrix ArrayIEEE Transactions on Semiconductor Manufacturing, 2004