Architectures for exponentiation in GF(2/sup m/)
Authors:
- S.J. SimmonsSSS.J. Simmons
- S.E. TavaresSTS.E. Tavares
- L.E. PeppardLPL.E. Peppard
- 1 April 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal on Selected Areas in Communications
- Vol. 6 (3) , 578-585
Abstract
Several VLSI architectures for performing exponentiation in GF(2 m) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2ei power, O⩽i⩽m-1, are precomputed and stored so that the intermediate product terms can be calculated in a parallel fashion. For the two approaches, both synchronous and asynchronous implementations are presented using standard and normal bases. The discussion emphasizes the design and performance tradeoffs incurred in developing such architecturesKeywords
This publication has 9 references indexed in Scilit:
- A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard basesIEEE Transactions on Computers, 1988
- Finite Fields for Computer Scientists and Engineers1987
- A Fast VLSI Multiplier for GF(2m)IEEE Journal on Selected Areas in Communications, 1986
- VLSI Architectures for Computing Multiplications and Inverses in GF(2m)IEEE Transactions on Computers, 1985
- Systolic Multipliers for Finite Fields GF(2m)IEEE Transactions on Computers, 1984
- The use of finite fields to compute convolutionsIEEE Transactions on Information Theory, 1975
- Polynomial Multiplication, Powers and Asymptotic Analysis: Some CommentsSIAM Journal on Computing, 1974
- A Cellular-Array Multiplier for GF(2m)IEEE Transactions on Computers, 1971
- Computation with finite fieldsInformation and Control, 1963