Theoretical Foundation for Upsets in CMOS Circuits Due to High-Power Electromagnetic Interference

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Abstract
The performance and reliability of CMOS integrated circuits are severely affected by high-power electromagnetic interference (EMI), resulting in serious operational upsets, critical bit errors, and reversible or irreversible failures. Based on experimental evidence from individual MOSFETs and CMOS cascaded inverters, the fundamental causes for such upsets are examined, and a new theoretical foundation based on excess charge effects and the nonlinear continuity equation for high level injection is developed. A new modified drain current MOSFET equation that includes the effects of EMI is proposed. The key experimental evidence that leads to the development of the theory and the validation of the theory are discussed. Comparisons between the experimental and calculated results based on the modified equation were found to be in excellent agreement. The modified MOSFET equation can now be used in the design, modeling, and simulation of CMOS ICs to predict vulnerabilities and to improve reliability and performance of CMOS electronic systems operating in critical and adverse environments.

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