Kyechong Kim

The performance and reliability of CMOS integrated circuits are severely affected by high-power electromagnetic interference (EMI), resulting in serious operational upsets, critical bit errors, and reversible or irreversible failures. Based on experimental evidence from individual MOSFETs and CMOS cascaded inverters, the fundamental causes for such upsets are examined, and a new theoretical foundation based on excess charge effects and the nonlinear continuity equation for high level injection is developed. A new modified drain current MOSFET equation that includes the effects of EMI is proposed. The key experimental evidence that leads to the development of the theory and the validation of the theory are discussed. Comparisons between the experimental and calculated results based on the modified equation were found to be in excellent agreement. The modified MOSFET equation can now be used in the design, modeling, and simulation of CMOS ICs to predict vulnerabilities and to improve reliability and performance of CMOS electronic systems operating in critical and adverse environments.

The effects of pulsed electromagnetic interference (PEMI) on the operational parameters of digital CMOS inverters, is reported. The characteristics of 1.5 mum and 0.5 mum inverters were measured with and without pulsed interference with respect to the characteristics of the pulses, as power was varied between 0 and 24 dBm, at frequencies of 1 GHz and 3 GHz. New bit-flip (from V_OH to V_OL) errors have been identified when the pulsed electromagnetic interference occurred at or below the threshold voltage of the MOSFET devices in the CMOS inverters. The bit-flip errors were observed to increase with narrower pulse widths and for the smaller devices, while for interference frequencies above 3 GHz, the power effects were found to be suppressed. The current transfer characteristics showed significant increase in the output current at the "ON" and "OFF" states of the inverters, which is found to be a critical vulnerability leading to catastrophic device failure due to metallization and interconnect failure. The comparison between measured current transfer characteristics of the 1.5 mum and 0.5 mum CMOS inverters under pulsed and CW interference and empirical channel mobility model showed that the observed output current increase had a weak dependence on thermal effects, suggesting that the electromagnetic interference effects are predominantly excess charge related.