Abstract
Voltage spikes caused by signal switching in adjacent circuits can lead to false switching and failures in integrated circuits. To identify such risks, signal integrity (SI) analysis is performed by extracting parasitic RC networks, followed by SPICE simulation or application of analytical methods. However, this process is time-consuming. This research proposes using machine learning methods to rapidly and accurately predict the results of SI analysis without the need for computationally expensive modeling. It accelerates SI analysis a lot with low accuracy losses. Also, this paper introduces new reduction model for victim-aggressor pair that is more accurate than previously used.

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