Dmitry Vladimirovich Telpukhov

This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language models with parameter-efficient fine-tuning—specifically, Low-Rank Adaptation and Quantized Low-Rank Adaptation—together with a specialized corpus of specification–code pairs that covers common design patterns and varying task complexity. The pipeline includes automated compilation, simulation, and synthesizability checks to ensure that outputs are both syntactically correct and suitable for downstream tool flows. Evaluation is performed using the pass-at-k metric on the standardized VerilogEval benchmark. The fine-tuned models substantially improve functional correctness over untuned baselines, achieving pass-at-k of up to 0.88 while markedly reducing both syntax and logic errors. The results indicate that reliable Verilog code generation from natural language can be achieved under constrained compute budgets; in our setup, effective training and inference remained feasible on a single graphics processing unit. Beyond empirical gains, the method demonstrates practical value for design automation by shortening iteration cycles and lowering the effort needed to move from textual requirements to synthesizable hardware modules. Overall, the findings support the use of large language models, paired with targeted data and validation, as a viable pathway for Verilog code generation and for accelerating the development of complex digital devices.

Nowadays, the problems of traffic accidents, inefficiency, and congestion still affect transportation systems. Conventional solutions often do not resolve and can even exacerbate the problems. Intelligent transportation system (ITS) technology, including intelligent vehicles, could provide a solution for these problems. However, such technologies should be thoroughly verified and validated before their large-scale adoption. Computer simulation can be used for this task to avoid the expenses of real-world testing. Modern consumer hardware computers are not powerful enough to handle large-scale scenes with high detail. Therefore, a parallel simulation approach employing multiple computers, each processing a separate scene of limited size, is proposed. To define the requirements for a suitable simulation tool, the needs of ITS simulation and Digital Twin technology are discussed, and existing simulation environments suitable for ITS technology verification and validation are evaluated. Further, an architecture for a parallel and multi-level simulation environment for large-scale detailed ITS modeling is proposed. The proposed integrated simulation environment uses the nanoscopic CARLA and microscopic SUMO simulators to implement multi-level and parallel nanoscopic simulation by creating a large scene on the microscopic simulation level and combining the information from multiple parallelly executed nanoscopic scenes. Special handling for nanoscopic scene logic is proposed using a concept of Buffer Zones that allows traffic participants to perceive environmental information beyond the logical boundary of the scene they belong to. The proposed approaches are demonstrated in a series of experiments as a proof of concept and are integrated into the CAVISE simulation environment.

This article explores the concept of low-level modeling of networks-on-chip (NoCs). A method for reducing the low-level NoC model by replacing the real IP blocks with a data packet generator module is proposed. This method is implemented in the low-level NoC modeling ECAD tool HDLNoCGen. This makes it possible to significantly increase the maximum number of nodes in the simulated NoC, as well as speed up the modeling and investigate the resource costs for network synthesis. A universal interface that can be used to connect new components to the network is also described. This interface has two main benefits: it reduces connection resource costs by eliminating the need to modify the connected component and shortens the time required to configure the connection interface itself. The proposed methodology of low-level NoC modeling is shown to be effective in analyzing the operation of routing algorithms of the NoC communication subsystem based on various topologies.

Voltage spikes caused by signal switching in adjacent circuits can lead to false switching and failures in integrated circuits. To identify such risks, signal integrity (SI) analysis is performed by extracting parasitic RC networks, followed by SPICE simulation or application of analytical methods. However, this process is time-consuming. This research proposes using machine learning methods to rapidly and accurately predict the results of SI analysis without the need for computationally expensive modeling. It accelerates SI analysis a lot with low accuracy losses. Also, this paper introduces new reduction model for victim-aggressor pair that is more accurate than previously used.

As part of the ICCAD Contest 2023 (Problem C) competition, the paper describes a methodology for applying ML models to perform static IR drop analysis. Methods for obtaining a database for training a neural network to solve this problem are given. We consider a technique for training an ML model to analyze the static IR-drop effect. The generation of input data for training a neural network from SPICE netlists is also discussed in this paper. This solution is ranked in the TOP 3 at the ICCAD Contest 2023 competition.

The paper explores the possibilities of using neural network methods to solve the problem of global routing for VLSI ASIC design. An algorithm has been developed for generating a training dataset based on the Lee algorithm, which allows one to synthesize three-dimensional matrices with obstacles and points that need to be connected. The U-Net fully convolutional neural network, effective for semantic segmentation of images, was selected for training. The quality of the results was assessed using a validation data. A significant reduction in routing time compared to the Lee algorithm was shown, but the share of unbroken routes was only 37%. Ways to improve the training dataset and adapt the approach to real conditions using DEF and GUIDE files are proposed. In general, the work demonstrated the potential of neural network methods to speed up the global routing task, but continued research is required to improve the quality and reliability of the results. The work is useful for specialists in the field of integrated circuit design and machine learning.

The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. In this paper, a method is proposed that develops the authors’ ideas based on the modified mixed-radix conversion and reference points. The modified method based on the mixed-radix conversion in this case makes it possible to replace the operation of finding the residue of division by a large modulo with the sequential calculation of the residue. The method of reference points allows to reduce the size of the stored information compared to the use of ROM to store all the residues of RNS. The application of this approach makes it possible to find a balance between the speed of the calculation and the hardware used, by varying the number of moduli of one method and the other.

Modern computational tasks are often required to not only guarantee predefined accuracy, but get the result fast. Optimizing calculations using floating point numbers, as opposed to integers, is a non-trivial task. For this reason, there is a need to explore new ways to improve such operations. This paper presents analysis and comparison of various floating point formats - float, posit and bfloat. One of the promising areas in which the problem of using such values can be considered to be the most acute is neural networks. That is why we pay special attention to algorithms of linear algebra and artificial intelligence to assess efficiency of new data types in this area. The research results showed that software implementations of posit16 and posit32 have high accuracy, but they are not particularly fast; on the other hand, bfloat16 is not much different from float32 in accuracy, but significantly surpasses it in performance for large amounts of data and complex machine learning algorithms. Thus, posit16 can be used in systems with less stringent performance requirements, as well as in conditions of limited computer memory; and also in cases when bfloat16 cannot provide required accuracy. As for bfloat16, it can speed up systems based on the IEEE 754 standard, but it cannot solve all the problems of conventional floating point arithmetic. Thus, although posits and bfloats are not a full fledged replacement for float, they provide (under certain conditions) advantages that can be useful for implementation of machine learning algorithms.