A routing algorithm for flip-chip design
Authors:
- Jia-Wei FangJFJia-Wei Fang
- I-Jye LinILI-Jye Lin
- Ping-Hung YuhPYPing-Hung Yuh
- Yao-Wen ChangYCYao-Wen Chang
- Jyh-Herng WangJWJyh-Herng Wang
- 22 December 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 753-758
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- A global routing method for 2-layer ball grid array packages2005
- Innovative Circuit Board Level Routing Designs for BGA PackagesIEEE Transactions on Advanced Packaging, 2004
- Min-cost flow-based algorithm for simultaneous pin assignment and routingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
- A flow based approach to the pin redistribution problem for multi-chip modules2002
- Pin assignment and routing on a single-layer pin grid array2002
- Automatic router for the pin grid array packageIEE Proceedings - Computers and Digital Techniques, 1999
- A performance-driven I/O pin routing algorithm1999
- NEWS: a net-even-wiring system for the routing on a multilayer PGA packageIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998
- On optimum single-row routingIEEE Transactions on Circuits and Systems, 1979