Abstract
Modern embedded heterogeneous Systems-on-Chip (SoCs) integrate differentiated memory hierarchy which require the programmer to undertake mostly simple, software-driven coherence protocols to optimize data-parallel applications. This paper presents a hybrid ring-based cache coherent multi-core architecture and a framework to develop memory hierarchy protocols customized to system constraints and workload needs. The ring protocol is developed in software over a typical mesh Network-on-Chip (NoC) which is used to convey cache coherent messages. Management and system monitoring operations utilize the NoC hardware routing protocol to achieve speed and minimize software interference and overheads. The software cache coherent management protocol lays on top of a typical shared memory programming model and facilitates easy user-level control and integration with user application, while removing concerns for data allocation for scratchpad-based systems.