George Kornaros

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

It is currently challenging to accomplish high data processing with low latency, because large-scale, persistent, high-bandwidth connection is often required to gather huge volumes of data from platforms and sensors operating at the edge to allow processing in the cloud. Internet-of-Things (IoT) devices deployment in remote locations for environmental monitoring with machine learning (ML) techniques, Internetof-Medical Things, IoT-based precision agriculture, all can operate with limited battery, while robustness and reliability is required. Machine learning algorithms employed in IoT devices improves efficiency as well as decision-making with real-time situational awareness and the capacity to react swiftly and accurately to impending actions or threats. This work presents a methodology to develop AI-based applications for Internet-ofThings environments by using the machine learning core inside the STM Mems Sensor LSM6DSOX and the toolchain Unico, Unicleo and WEKA. In particular, we demonstrate an efficient implementation that combines the target IoT platform's compilation toolchain and platform-specific resource limitations into the model selection process, to leverage embedded hardware machine learning for automated monitoring of the detection of a falling object.

As the Internet of Things (IoT) technology advances, billions of multidisciplinary smart devices act in concert, rarely requiring human intervention, posing significant challenges in supporting trusted computing and user privacy, as well as protecting against attacks such as spoofing, denial of service (DoS), jamming, and eavesdropping. To tackle attacks on the IoT and cyber-physical ecosystem, many intrusion detection and security approaches have been presented in the literature. Machine learning (ML) based intrusion and anomaly detection has lately gained traction due to its capacity to cope with encrypted and rapidly developing threat techniques. This work investigates into machine learning (ML) and deep learning (DL) methodologies for IoT device security and examine the benefits, drawbacks, and potential. To protect an IoT infrastructure, various solutions look into hardware-based methods for ML-based IoT authentication, access control, secure offloading, and malware detection schemes. This review aims to illuminate the value of various approaches for addressing IoT security in a truly effective, flexible, and seamless manner, as well as to provide answers to questions about tradeoffs in integrating accelerators and customizing embedded device architectures for effective use of ML-based methods.

Modern embedded heterogeneous Systems-on-Chip (SoCs) integrate differentiated memory hierarchy which require the programmer to undertake mostly simple, software-driven coherence protocols to optimize data-parallel applications. This paper presents a hybrid ring-based cache coherent multi-core architecture and a framework to develop memory hierarchy protocols customized to system constraints and workload needs. The ring protocol is developed in software over a typical mesh Network-on-Chip (NoC) which is used to convey cache coherent messages. Management and system monitoring operations utilize the NoC hardware routing protocol to achieve speed and minimize software interference and overheads. The software cache coherent management protocol lays on top of a typical shared memory programming model and facilitates easy user-level control and integration with user application, while removing concerns for data allocation for scratchpad-based systems.

Today, the growth of automotive networking services such as Vehicle-to-Vehicle and Vehicle-to-Infrastructure along with services such as self-driving and advanced driver assistance systems is accompanied with significant security concerns. This work introduces virtual sensors by extending vehicle’s gateway functionality with supervised machine learning to monitor temporal behavior of CAN bus messages. Even though advanced machine learning algorithms are barely used for a vehicular network because the computing power of the conventional Electronic Control Unit is limited to tackle the complex process, we design and demonstrate a vehicle gateway enabled with k-NN classification to achieve real-time analysis of traffic from three fully loaded CAN buses for secure vehicle networking.

Emerging heterogeneous systems architectures increasingly integrate general-purpose processors, GPUs, and other specialized computational units to provide both power and performance benefits. While the motivations for developing systems with accelerators are clear, it is important to design efficient dispatching mechanisms in terms of performance and energy while leveraging programmability and orchestration of the diverse computational components. In this article we present an infrastructure composed of a hardware, General, Packet-based Processing-dispatching Unit, named GPPU, and of an associated runtime that facilitates user-level access to GPPU objects such as packets, queues and contexts. Hence, we remove drawbacks of traditional costly user-to-kernel-level operations, low-level accelerator subtleties that hinder programming productivity, along with architectural obstacles such as handling accelerators’ unified virtual address space. We present the design and evaluation of our framework by integrating the GPPU infrastructure with data streaming type accelerators, image filtering and matrix multiplication, tightly coupled to ARMv8 architecture via unified virtual memory. Under scaling workload our proposed dispatching methods can deliver 3.7× performance improvement over baseline offloading, and up to 4.7× better energy efficiency.