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Publications
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
Publication with shared reference
10.1145/1687399.1687434
Home
Publications
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
Publication with shared reference
10.1145/1687399.1687434
Publications with shared reference:
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
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