Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Authors:

Open Access

2 November 2009

conference paper
Published by Association for Computing Machinery (ACM)

p. 191-196
DOI:10.1145/1687399.1687434

Abstract

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.

Keywords

Funding Information

National Natural Science Foundation of China (60876029, N CUHK417/08)
Research Grants Council, University Grants Committee, Hong Kong (CUHK418708, N CUHK417/08, CUHK417406CUHK417807)
Ministry of Science and Technology of the People's Republic of China (2007AA01Z109)

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