Jeffrey C. Suhling

This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm² using only a 1.5 μm process. The arrays are sequentially scanned by an on-chip counter, producing efficient stress measurement, and the sensors resolve normal and shear stresses on the surface of the die with resolution below 1 MPa. The CMOS sensor chips have been used to map stress over a large portion of the die in chip-on-beam and encapsulated chip-on-beam samples, as well as a ceramic dual-in-line package with its cavity filled with underfill material. Finite-element simulation results correlate well with the measured stress distributions. The experimental results from these chips are used to validate finite-element simulation models, and the array designs can be used as subarrays in much larger test chips.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects (Ma, et al., ECTC 2006), we demonstrated that the observed material behavior variations of SAC405 and SAC305 lead free solders during room temperature aging (25 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are much more dramatic at the higher aging temperatures (e.g. 100–150 °C) typical of the harsh environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have explored the effects of elevated temperature isothermal aging on the mechanical behavior and reliability of lead free solders. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on SAC405 and SAC305 samples that were aged for various durations (0–6 months) at several elevated temperatures (80, 100, 125, and 150 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and temperature. In this paper, we have concentrated our efforts on presenting the results for samples aged at 125 °C. In addition, the new elevated temperature aging data were correlated with our room temperature results from last year’s investigation. The results obtained in this work have demonstrated the significant effects of elevated temperature exposure on solder joints. As expected, the mechanical properties evolved at a higher rate and experienced larger changes during elevated temperature aging (compared to room temperature aging). After approximately 200 hours of aging, the lead free solder joint material properties were observed to degrade at a nearly constant rate. We have developed a mathematical model to predict the variation of the properties with aging time and aging temperature. Our data for the evolution of the creep response of solders with elevated temperature aging show that the creep behavior of lead free and tin-lead solders experience a “crossover point” where lead free solders begin to creep at higher rates than standard 63Sn-37Pb solder for the same stress level. Such an effect is not observed for solder joints aged at room temperature, where SAC alloys always creep at lower rates than Sn-Pb solder.

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

This paper reports high resolution die stress measurements using a multiplexed array of 512 current mirror type CMOS piezoresistive FET stress sensor cells fabricated on an MOSIS tiny chip. Using 1.5 μm CMOS technology, a stress mapping resolution of 256 points/mm2 has been obtained, providing high spatial resolution mapping of the stress on the surface of the integrated circuit die. Driven by an on-chip counter, the sequentially scanned array efficiently maps the two-dimensional stress field. The sensor array is calibrated using a chip-on-beam calibration technique. These CMOS sensor arrays have been used to map stress on the die in the chip-on-beam configuration under four-point-bending load, in encapsulated chip-on-beam samples, and in DIP40 packages with cavities filled with underfill. The measured stress distribution agrees well with finite element simulation results, and permit smooth measurement of stress gradients on the surface of the integrated circuit die. The results give clear verification that the NMOS PiFET sensors are indeed responding to shear stresses.

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.