Richard C. Jaeger

In the past, silicon has been one of the main materials used in piezoresistive stress sensors. However, Si based sensors are not capable of operating at high temperature due to its relatively low bandgap energy (1.12 eV). On the other hand, the bandgap of 4H silicon carbide (4H-SiC) is 3.23 eV, which can effectively reduce the number of electron-hole pairs generated in high

In the past, silicon has been one of the main materials used in piezoresistive stress sensors. However, Si based sensors are not capable of operating at high temperature due to its relatively low bandgap energy (1.12 eV). On the other hand, the bandgap of 4H-SiC is 3.23 eV, which can effectively reduce the number of electron-hole pairs generated in high temperature across the

The conjecture discussed in our previous paper [Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., 2014, “Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors,” ASME J. Electron. Packag., 136(4), p. 041014; Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., 2018, Erratum: “Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors,” ASME J. Electron. Packag., 140(1), p. 017001] was backed up by measurements and simulation results, but not mathematically proven. A proof based upon two-port impedance parameter reciprocity is presented with additional experimental confirmation.

This paper reports the design, calibration and application of multiplexed arrays of piezoresistive field-effect transistor stress sensors fabricated in a standard complementary-metal-oxide semiconductor (CMOS) process. Two complementary arrays of 256-current mirror sensor cells provide high spatial density stress mapping with approximately 300 pts/mm² using only a 1.5 μm process. The arrays are sequentially scanned by an on-chip counter, producing efficient stress measurement, and the sensors resolve normal and shear stresses on the surface of the die with resolution below 1 MPa. The CMOS sensor chips have been used to map stress over a large portion of the die in chip-on-beam and encapsulated chip-on-beam samples, as well as a ceramic dual-in-line package with its cavity filled with underfill material. Finite-element simulation results correlate well with the measured stress distributions. The experimental results from these chips are used to validate finite-element simulation models, and the array designs can be used as subarrays in much larger test chips.

Stress sensing test chips are used to investigate die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are able to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensors fabricated on the surface of the (111) silicon wafers offer the advantage of being able to measure the complete stress state compared to such sensors fabricated on the (100) silicon. However, complete calibration of the three independent piezoresistive coefficients is more difficult and one approach utilizes hydrostatic measurement of the silicon “pressure” coefficients. We are interested in stress measurements over a very broad range of temperatures, and this paper present the experimental methods and results for hydrostatic measurements of the pressure coefficient of both n- and p-type silicon over a wide range of temperatures and then uses the results to provide a complete set of temperature dependent piezoresisitive coefficients for the (111) silicon.

This paper reports high resolution die stress measurements using a multiplexed array of 512 current mirror type CMOS piezoresistive FET stress sensor cells fabricated on an MOSIS tiny chip. Using 1.5 μm CMOS technology, a stress mapping resolution of 256 points/mm2 has been obtained, providing high spatial resolution mapping of the stress on the surface of the integrated circuit die. Driven by an on-chip counter, the sequentially scanned array efficiently maps the two-dimensional stress field. The sensor array is calibrated using a chip-on-beam calibration technique. These CMOS sensor arrays have been used to map stress on the die in the chip-on-beam configuration under four-point-bending load, in encapsulated chip-on-beam samples, and in DIP40 packages with cavities filled with underfill. The measured stress distribution agrees well with finite element simulation results, and permit smooth measurement of stress gradients on the surface of the integrated circuit die. The results give clear verification that the NMOS PiFET sensors are indeed responding to shear stresses.

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 × 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. The test chips incorporate resistor or transistor sensing elements that are able to measure stresses by observing the changes in their resistivity or carrier mobility. This piezoresistive behavior of such sensors is characterized by three piezoresistive coefficients, which are electro-mechanical material constants. We are interested in stress characterization over a very broad range of temperatures. However, the literature provides limited data over the desired range, and even the data at room temperature, exhibit wide discrepancies in magnitude as well as sign. This work focuses on an extensive experimental study of the temperature dependence of the piezoresistive coefficients, π11, π12, and π44, for both p- and n-type silicon. In order to minimize errors associated with misalignment with the crystallographic axes on (100) silicon wafers, anisotropic wet etching was used in this work to accurately locate the axes. A special four-point bending apparatus has been constructed and integrated into an environmental chamber capable of temperatures from −155 to +300°C. Experimental calibration results for the piezoresistive coefficients as a function of temperature from −150°C to +125°C are presented and compared and contrasted with existing values from literature. Measurements were performed using stress sensors fabricated on (100) silicon mounted on PCB material including both die-on-beam and strip-on-beam mounting techniques. Four-point bending (4PB) was used to generate the required stress, and finite element simulations have been used to determine the actual states of stress in the silicon material.

Wafer-level and four-point-bending (4PB) techniques are normally utilized for calibration of stress sensor test die. While excellent accuracy and repeatability have been demonstrated, the wafer-level technique requires access to a complete silicon wafer, whereas the 4PB method requires 5–10 cm strips of die. However, access to full wafers, or even strips of die, is typically limited to companies and universities with captive semiconductor fabrication facilities. In this paper, a chip-on-beam technique is demonstrated in which individual die are attached to silicon beams, and stress for calibration is applied to the beam using a precision 4PB fixture. Because of the resulting nonuniform stress distribution on the surface of the die, experimental measurements must be combined with finite element simulation results to extract the desired piezoresistive coefficients. These calibration results are compared to those obtained directly from strips of the same die, and it is shown that excellent agreement can be obtained between the two methods under proper experimental conditions. This work delineates the best location for calibration rosettes on the die as well as design of the beam geometry, relative to the chip dimensions, that will ensure the high accuracy calibration results. This technique permits measurement of the piezoresistive coefficients for a limited set of die such as those that may be obtained from typical MOSIS fabrication runs.