Marcus Ahles
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Marcus Ahles has a total of 3 co-authors. Here are the top co-authors by number of shared publications:
- Heinz von Seggern
Department of Materials and Earth Sciences Technical University of Darmstadt 25 Merck St 64283 Darmstadt Germany
2 shared publications - Roland Schmechel
University of Duisburg-Essen
2 shared publications Aline Hepp
Institute of Materials Science, Darmstadt University of Technology, Petersenstrasse 23, 64287 Darmstadt, Germany
1 shared publication
Latest Publications
- 9 September 2005
- Published by AIP Publishing in Applied Physics Letters
- Vol. 87 (11) , 113505
Complementary inverter based on interface doped pentacene
An organic complementary metal–oxide–semiconductor (O-CMOS) inverter is presented, which is based on a single pentacene layer acting both as n- and p-type organic semiconductors. The circuit consists of two spatially separated transistors realized by pairs of calcium and gold source and drain electrodes, respectively. The p transistor is obtained by utilizing the conventional pentacene∕SiO2 channel interface whereas the n transistor is realized by doping the SiO2 interface with traces of calcium prior to pentacene deposition. Both, n and p transistors work exclusively in unipolar mode within the range of the supply voltage of 60 V. The O-CMOS inverter works reliably with a gain in between 17 and 24, and the respective electron and hole mobilities were found around 0.1cm2V−1s−1. The circuit shows hysteresis, which can be explained by a gate voltage-dependent electron trapping in the n channel. Electron accumulation can also be realized by the application of a polymethylmethacrylate interlayer between SiO2 and pentacene.
- 9 September 2005
- Published by AIP Publishing in Applied Physics Letters
- Vol. 87 (11) , 113505
Complementary inverter based on interface doped pentacene
An organic complementary metal–oxide–semiconductor (O-CMOS) inverter is presented, which is based on a single pentacene layer acting both as n- and p-type organic semiconductors. The circuit consists of two spatially separated transistors realized by pairs of calcium and gold source and drain electrodes, respectively. The p transistor is obtained by utilizing the conventional pentacene∕SiO2 channel interface whereas the n transistor is realized by doping the SiO2 interface with traces of calcium prior to pentacene deposition. Both, n and p transistors work exclusively in unipolar mode within the range of the supply voltage of 60 V. The O-CMOS inverter works reliably with a gain in between 17 and 24, and the respective electron and hole mobilities were found around 0.1cm2V−1s−1. The circuit shows hysteresis, which can be explained by a gate voltage-dependent electron trapping in the n channel. Electron accumulation can also be realized by the application of a polymethylmethacrylate interlayer between SiO2 and pentacene.
- 19 January 2004
- Published by AIP Publishing in Applied Physics Letters
- Vol. 84 (3) , 428-430
Light emission from a polymer transistor
We report on light emission from a polymeric transistor that utilizes interdigitated source and drain electrodes with channel length of 5 μm in a bottom gate configuration based on a substrate. The polymer investigated is poly[9,9-di(ethylhexyl)fluorene] deposited by spin coating from chloroform solution to achieve an active layer thickness of 40 nm. Light emission occurs above drain source voltages of −60 V and the light intensity can be controlled by the gate voltage. Emission occurs close to the drain electrode as determined by optical microscopy. The transistor operates in hole accumulation mode without saturation of the output characteristics.- 19 January 2004
- Published by AIP Publishing in Applied Physics Letters
- Vol. 84 (3) , 428-430
Light emission from a polymer transistor
We report on light emission from a polymeric transistor that utilizes interdigitated source and drain electrodes with channel length of 5 μm in a bottom gate configuration based on a substrate. The polymer investigated is poly[9,9-di(ethylhexyl)fluorene] deposited by spin coating from chloroform solution to achieve an active layer thickness of 40 nm. Light emission occurs above drain source voltages of −60 V and the light intensity can be controlled by the gate voltage. Emission occurs close to the drain electrode as determined by optical microscopy. The transistor operates in hole accumulation mode without saturation of the output characteristics.