He Guan
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
He Guan has a total of 99 co-authors. Here are the top co-authors by number of shared publications:
- Ying Wang
School of Microelectronics, Northwestern Polytechnical University, Xian, China
6 shared publications - Yongchuan Tang
School of Integrated Circuits and Microelectronics, Northwestern Polytechnical University, Xi’an 710072, China
5 shared publications - Chengyu Jiang
School of Electronics and Information, Northwestern Polytechnical University, Xi’an 710129, China
3 shared publications - Shaoxi Wang
School of Microelectronics, Northwestern Polytechnical University, Xi’an 710072, China
3 shared publications - Ziqiang Zeng
School of Microelectronics, Northwestern Polytechnical University (NWPU), Xian, China
3 shared publications Borui Deng
School of Microelectronics, Northwestern Polytechnical University (NWPU), Xian, China
2 shared publications
Latest Publications
- Open Access
- 12 October 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (10) , 1181
Decoupled Multiplicative Physics-Guided Neural Network for Extrapolative Modeling of GaN HEMT
Rapid direct-current (DC) surrogate modeling of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) requires accurate prediction of the current-capability, conduction-loss, and self-heating indicators used in geometry screening. This work presents an electrothermal decoupled multiplicative physics-guided neural network (ET-DM-PGNN) for this task. It combines a gray-box backbone, separate high- and low-field polarization channels, a latent DC self-heating update, and bounded target-specific multiplicative residuals. A two-stage strategy first calibrates the complete surrogate and then refines the current branch while preserving resistance and temperature. On 32 interstitial samples, ET-DM-PGNN achieves , with mean absolute percentage errors of 0.13%, 0.15%, and 0.04% for , , and , respectively. The corresponding errors on nine external cases are 1.46%, 0.94%, and 0.74%. A leakage-controlled, three-seed level-held-out audit yields errors of 0.44–6.40% in four composition and lateral-geometry directions, whereas holding out the 0.015 µm barrier level produces errors of 12.41–21.21% under the tested training protocol. Across 365 geometries, 4 updates differ from a 12-step reference by at most 0.0076%. Numerically validated at V using TCAD DC sweeps extending to V, the surrogate supports rapid fixed-protocol geometry screening and identifies the ultrathin-barrier direction as the least reliable tested extrapolation regime.- 12 October 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (10) , 1181
Open AccessDecoupled Multiplicative Physics-Guided Neural Network for Extrapolative Modeling of GaN HEMT
Rapid direct-current (DC) surrogate modeling of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) requires accurate prediction of the current-capability, conduction-loss, and self-heating indicators used in geometry screening. This work presents an electrothermal decoupled multiplicative physics-guided neural network (ET-DM-PGNN) for this task. It combines a gray-box backbone, separate high- and low-field polarization channels, a latent DC self-heating update, and bounded target-specific multiplicative residuals. A two-stage strategy first calibrates the complete surrogate and then refines the current branch while preserving resistance and temperature. On 32 interstitial samples, ET-DM-PGNN achieves , with mean absolute percentage errors of 0.13%, 0.15%, and 0.04% for , , and , respectively. The corresponding errors on nine external cases are 1.46%, 0.94%, and 0.74%. A leakage-controlled, three-seed level-held-out audit yields errors of 0.44–6.40% in four composition and lateral-geometry directions, whereas holding out the 0.015 µm barrier level produces errors of 12.41–21.21% under the tested training protocol. Across 365 geometries, 4 updates differ from a 12-step reference by at most 0.0076%. Numerically validated at V using TCAD DC sweeps extending to V, the surrogate supports rapid fixed-protocol geometry screening and identifies the ultrathin-barrier direction as the least reliable tested extrapolation regime. - Open Access
- 10 April 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (4) , 462
A K-Band Four-Channel Beamformer with Temperature Compensation Based on 65 nm CMOS Process
This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm2, the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel.
- 10 April 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (4) , 462
Open AccessA K-Band Four-Channel Beamformer with Temperature Compensation Based on 65 nm CMOS Process
This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm2, the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel.
- 24 March 2026
- Published by IOP Publishing in Physica Scripta
- Vol. 101 (15)
Device-level electro-thermal co-optimization of the InP based terahertz sources
This study employs a systematic numerical investigation framework centered on TCAD simulation to address thermal management challenges in InP-based In0.53Ga0.47As planar Gunn diodes. Through comprehensive two-dimensional thermal-electrical co-simulation, we evaluate substrate materials (InP, Si, diamond) and thermal films (diamond, graphene) on device performance. The simulation results indicate that the diamond substrate can significantly reduce the operating temperature of the device, increase the oscillation frequency, and enhance the output power. Both diamond and graphene thermal films effectively mitigate thermal resistance, improving output characteristics through temperature reduction exceeding 150 K. Furthermore, we propose a novel diamond-graphene composite thermal management structure that achieves a significant temperature reduction from 607.3 K to 373.3 K (ΔT = 234 K), simultaneously enhancing oscillation frequency to 203.6 GHz and power conversion efficiency to 0.80%. These findings establish material-driven thermal optimization principles for high-frequency terahertz sources, suggesting significant potential for device performance enhancement.
- 24 March 2026
- Published by IOP Publishing in Physica Scripta
- Vol. 101 (15)
Device-level electro-thermal co-optimization of the InP based terahertz sources
This study employs a systematic numerical investigation framework centered on TCAD simulation to address thermal management challenges in InP-based In0.53Ga0.47As planar Gunn diodes. Through comprehensive two-dimensional thermal-electrical co-simulation, we evaluate substrate materials (InP, Si, diamond) and thermal films (diamond, graphene) on device performance. The simulation results indicate that the diamond substrate can significantly reduce the operating temperature of the device, increase the oscillation frequency, and enhance the output power. Both diamond and graphene thermal films effectively mitigate thermal resistance, improving output characteristics through temperature reduction exceeding 150 K. Furthermore, we propose a novel diamond-graphene composite thermal management structure that achieves a significant temperature reduction from 607.3 K to 373.3 K (ΔT = 234 K), simultaneously enhancing oscillation frequency to 203.6 GHz and power conversion efficiency to 0.80%. These findings establish material-driven thermal optimization principles for high-frequency terahertz sources, suggesting significant potential for device performance enhancement.
- Open Access
- 10 March 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (3) , 338
A 6–18 GHz High-Efficiency GaN Power Amplifier Using Transistor Stacking and Reactive Matching
This article presents the design and implementation of a 6–18 GHz GaN monolithic microwave integrated circuit (MMIC) power amplifier (PA). A two-stage cascaded reactive matching network structure based on transistor stacking technology is employed to achieve circuit gain, and a multi-cell combination is used in the final stage to simultaneously achieve high power and high efficiency. For demonstration, a prototype of the proposed PA with an area of 4.5 × 3.4 mm2 is fabricated in a 0.1 µm GaN-on-Si high-electron-mobility transistor (HEMT) process. The measured results of the GaN PA show a small signal gain of 25–29 dB, an output power of 40.8–42.5 dBm, and a power-added efficiency (PAE) of 27–38% in the operating frequency range of 6–18 GHz.
- 10 March 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (3) , 338
Open AccessA 6–18 GHz High-Efficiency GaN Power Amplifier Using Transistor Stacking and Reactive Matching
This article presents the design and implementation of a 6–18 GHz GaN monolithic microwave integrated circuit (MMIC) power amplifier (PA). A two-stage cascaded reactive matching network structure based on transistor stacking technology is employed to achieve circuit gain, and a multi-cell combination is used in the final stage to simultaneously achieve high power and high efficiency. For demonstration, a prototype of the proposed PA with an area of 4.5 × 3.4 mm2 is fabricated in a 0.1 µm GaN-on-Si high-electron-mobility transistor (HEMT) process. The measured results of the GaN PA show a small signal gain of 25–29 dB, an output power of 40.8–42.5 dBm, and a power-added efficiency (PAE) of 27–38% in the operating frequency range of 6–18 GHz.
- 12 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 74 (3) , 2367-2381
Synthesis of Wideband High-Selectivity Bandpass Filter Based on Tri-Mode Lumped-Element Resonators in Heterogeneous LTCC Substrate
In this article, we propose a synthesis method for wideband high-selectivity bandpass filters (BPFs) based on the tri-mode lumped-element resonator in heterogeneous low-temperature co-fired ceramic (LTCC) substrates. The tri-mode lumped-element resonator is analyzed to generate three resonances and two controllable transmission zeros without using cross couplings, showing a simple topology. A Remez-like numerical iterative algorithm is adopted to construct the polynomials of the tri-mode resonator in the bandpass domain, which can eliminate the need for complex transmission-function polynomial derivations and high-order iterations, allowing direct calculation of lumped-element values by the polynomials without optimization. Furthermore, the extracted-pole technique is used to expand the filter design. A comprehensive synthesis workflow is proposed for high-order filtering responses by integrating the extracted-pole technique and the tri-mode lumped-element resonator. The resultant filter is capable of achieving the desired responses with a wide bandwidth and multiple transmission zeros in a simple and practically achievable topology. For demonstration, a BPF covering 5G-n77 band (3.3–4.2 GHz) is implemented using a heterogeneous LTCC substrate. The measured result shows a low loss of 0.76dB and the circuit size is only $1.3\times 1.09\times 0.53$ mm3 (or $0.016\lambda _{{0}} \times 0.014\lambda _{{0}} \times 0.007\lambda _{{0}}$ ), which is suitable for 5G applications.
- 12 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 74 (3) , 2367-2381
Synthesis of Wideband High-Selectivity Bandpass Filter Based on Tri-Mode Lumped-Element Resonators in Heterogeneous LTCC Substrate
In this article, we propose a synthesis method for wideband high-selectivity bandpass filters (BPFs) based on the tri-mode lumped-element resonator in heterogeneous low-temperature co-fired ceramic (LTCC) substrates. The tri-mode lumped-element resonator is analyzed to generate three resonances and two controllable transmission zeros without using cross couplings, showing a simple topology. A Remez-like numerical iterative algorithm is adopted to construct the polynomials of the tri-mode resonator in the bandpass domain, which can eliminate the need for complex transmission-function polynomial derivations and high-order iterations, allowing direct calculation of lumped-element values by the polynomials without optimization. Furthermore, the extracted-pole technique is used to expand the filter design. A comprehensive synthesis workflow is proposed for high-order filtering responses by integrating the extracted-pole technique and the tri-mode lumped-element resonator. The resultant filter is capable of achieving the desired responses with a wide bandwidth and multiple transmission zeros in a simple and practically achievable topology. For demonstration, a BPF covering 5G-n77 band (3.3–4.2 GHz) is implemented using a heterogeneous LTCC substrate. The measured result shows a low loss of 0.76dB and the circuit size is only $1.3\times 1.09\times 0.53$ mm3 (or $0.016\lambda _{{0}} \times 0.014\lambda _{{0}} \times 0.007\lambda _{{0}}$ ), which is suitable for 5G applications.
- 6 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 74 (4) , 3414-3425
A 24–30-GHz GaN-on-SiC T/R Front-End Module With 37.5-dBm Output Power and 32% Peak PAE Based on Second-Harmonic Control Technique
This article presents a 24–30-GHz wideband transmit–receive (T/R) front-end module (FEM) for 5G millimeter-wave (mm-Wave) applications in the 150-nm GaN-on-SiC HEMT process. The power amplifier in the transmitting chain is constructed of two fully symmetrical push–pull amplifiers that are designed using transformer-based baluns. To improve efficiency, the harmonic control technique is used in the output impedance matching network, where the second-harmonic impedance can be optimized without affecting the fundamental response. A high-order stacked-transistor single-pole double-throw (SPDT) switch is designed with a low insertion loss of 0.75dB and a high input 1-dB compression point (IP ${}_{\mathrm {1dB}}$ ) of over 44dBm, ensuring almost no gain compression in transmitting mode. The low-noise amplifier (LNA) in the receiving chain is designed into a three-stage topology, achieving a flat gain and low-noise figure (NF) within the operating bandwidth. In measurements, the proposed FEM operating across 24–30 GHz demonstrates a maximum saturated power ( $P_{\mathrm {sat}}$ ) of 37.5dBm and peak power-added efficiency (PAE) of 32% in the transmitting mode. An error vector magnitude (EVM) of 5.75% and an average output power of 25.7 dBm with a 64-quadrature amplitude modulation (QAM) 5G FR2 modulated signal of 100-MHz bandwidth at 27 GHz are realized. In the receiving mode, the FEM demonstrates a NF of less than 3.1 dB, a flat small-signal gain of 20–21.3 dB, and an output 1-dB compression point (OP ${}_{\mathrm {1dB}}$ ) of 20.4 dBm.
- 6 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 74 (4) , 3414-3425
A 24–30-GHz GaN-on-SiC T/R Front-End Module With 37.5-dBm Output Power and 32% Peak PAE Based on Second-Harmonic Control Technique
This article presents a 24–30-GHz wideband transmit–receive (T/R) front-end module (FEM) for 5G millimeter-wave (mm-Wave) applications in the 150-nm GaN-on-SiC HEMT process. The power amplifier in the transmitting chain is constructed of two fully symmetrical push–pull amplifiers that are designed using transformer-based baluns. To improve efficiency, the harmonic control technique is used in the output impedance matching network, where the second-harmonic impedance can be optimized without affecting the fundamental response. A high-order stacked-transistor single-pole double-throw (SPDT) switch is designed with a low insertion loss of 0.75dB and a high input 1-dB compression point (IP ${}_{\mathrm {1dB}}$ ) of over 44dBm, ensuring almost no gain compression in transmitting mode. The low-noise amplifier (LNA) in the receiving chain is designed into a three-stage topology, achieving a flat gain and low-noise figure (NF) within the operating bandwidth. In measurements, the proposed FEM operating across 24–30 GHz demonstrates a maximum saturated power ( $P_{\mathrm {sat}}$ ) of 37.5dBm and peak power-added efficiency (PAE) of 32% in the transmitting mode. An error vector magnitude (EVM) of 5.75% and an average output power of 25.7 dBm with a 64-quadrature amplitude modulation (QAM) 5G FR2 modulated signal of 100-MHz bandwidth at 27 GHz are realized. In the receiving mode, the FEM demonstrates a NF of less than 3.1 dB, a flat small-signal gain of 20–21.3 dB, and an output 1-dB compression point (OP ${}_{\mathrm {1dB}}$ ) of 20.4 dBm.
- Open Access
- 17 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of the Electron Devices Society
- Vol. 13, 1158-1167
Enhanced Low-Damage Quantitative Hybrid Cyclic Etching for AlGaN/GaN Heteroepitaxy: Process Optimization and Device Performance Improvement
The etching process is pivotal in the fabrication of GaN-based devices, directly influencing their performance. This study presents an enhanced low-damage hybrid cyclic etching technology for AlGaN/GaN heteroepitaxy structures, combining oxygen plasma oxidation with HCl etching to achieve atomic-scale precision. By carefully controlling the oxidation layer thickness, this method preserves a low surface roughness of 0.228 nm and achieves an etching rate of 0.45 nm/cycle with excellent consistency. Compared to conventional ICP dry etching and KOH wet etching evaluated under identical experimental conditions, the proposed technique significantly reduces etching-induced-damage. When applied to the ohmic contact formation of AlGaN/GaN HEMTs using the same metallization scheme and annealing process, devices fabricated with the new hybrid etching method demonstrated a significantly lower contact resistance of 0.76 Ω7mm compared to those using conventional ICP etching (1.21 Ω7mm) or no additional etching after SiN removal (1.37 Ω7mm). Furthermore, these devices exhibited a threshold voltage of -6.5 V, a saturation drain current density of 880.55 mA/mm, and a knee voltage of approximately 4 V. This method also demonstrates potential for recessed gate etching and post-dry-etching damage repair, offering a promising solution for low-roughness surfaces processing with broad application prospects.
- 17 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of the Electron Devices Society
- Vol. 13, 1158-1167
Open AccessEnhanced Low-Damage Quantitative Hybrid Cyclic Etching for AlGaN/GaN Heteroepitaxy: Process Optimization and Device Performance Improvement
The etching process is pivotal in the fabrication of GaN-based devices, directly influencing their performance. This study presents an enhanced low-damage hybrid cyclic etching technology for AlGaN/GaN heteroepitaxy structures, combining oxygen plasma oxidation with HCl etching to achieve atomic-scale precision. By carefully controlling the oxidation layer thickness, this method preserves a low surface roughness of 0.228 nm and achieves an etching rate of 0.45 nm/cycle with excellent consistency. Compared to conventional ICP dry etching and KOH wet etching evaluated under identical experimental conditions, the proposed technique significantly reduces etching-induced-damage. When applied to the ohmic contact formation of AlGaN/GaN HEMTs using the same metallization scheme and annealing process, devices fabricated with the new hybrid etching method demonstrated a significantly lower contact resistance of 0.76 Ω7mm compared to those using conventional ICP etching (1.21 Ω7mm) or no additional etching after SiN removal (1.37 Ω7mm). Furthermore, these devices exhibited a threshold voltage of -6.5 V, a saturation drain current density of 880.55 mA/mm, and a knee voltage of approximately 4 V. This method also demonstrates potential for recessed gate etching and post-dry-etching damage repair, offering a promising solution for low-roughness surfaces processing with broad application prospects.
- 22 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (6) , 2718-2724
Multiscenario Coupled Model of GaN-on-Si HEMTs Epitaxial Design and Performance Improvement Based on Multiobjective Optimization Method
Gallium nitride high-electron mobility transistors (GaN-on-Si HEMTs) on silicon substrates exhibit significant potential in the field of radio frequency devices due to its high frequency, high-speed, and low-cost advantages. Nevertheless, the thermal stress caused by the mismatch in lattice parameters and the coefficient of thermal expansion between the Si substrate and GaN epitaxial layer constrains the device performance. Due to different temperature distributions in different scenarios, there is an urgent need for a model that can balance the contradiction between epitaxial growth and device operation for the joint design of GaN-on-Si HEMTs’ epitaxial structures. This work presents thermal stress formulas specifically designed for GaN epitaxial growth and device operation, based on Townsend’s theory of multilayer film curvature and stress. Furthermore, our work innovatively proposes a multiscenario coupled GaN-on-Si HEMTs’ epitaxial structure design model based on multiobjective optimization. The model represents a combined objective function incorporating thermal stress experienced during device operation and epitaxial growth, as well as the total thermal resistance and bulk thermal conductivity of the epitaxial layer. Through simulation validation, the model has been proved to effectively calculate the optimized epitaxial structure parameters across multiple scenarios to meet diverse requirements. And it can effectively reduce the operating temperature. This model can accelerate the process of GaN epitaxial design and provide an effective method for enhancing the performance of GaN-on-Si HEMTs.
- 22 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (6) , 2718-2724
Multiscenario Coupled Model of GaN-on-Si HEMTs Epitaxial Design and Performance Improvement Based on Multiobjective Optimization Method
Gallium nitride high-electron mobility transistors (GaN-on-Si HEMTs) on silicon substrates exhibit significant potential in the field of radio frequency devices due to its high frequency, high-speed, and low-cost advantages. Nevertheless, the thermal stress caused by the mismatch in lattice parameters and the coefficient of thermal expansion between the Si substrate and GaN epitaxial layer constrains the device performance. Due to different temperature distributions in different scenarios, there is an urgent need for a model that can balance the contradiction between epitaxial growth and device operation for the joint design of GaN-on-Si HEMTs’ epitaxial structures. This work presents thermal stress formulas specifically designed for GaN epitaxial growth and device operation, based on Townsend’s theory of multilayer film curvature and stress. Furthermore, our work innovatively proposes a multiscenario coupled GaN-on-Si HEMTs’ epitaxial structure design model based on multiobjective optimization. The model represents a combined objective function incorporating thermal stress experienced during device operation and epitaxial growth, as well as the total thermal resistance and bulk thermal conductivity of the epitaxial layer. Through simulation validation, the model has been proved to effectively calculate the optimized epitaxial structure parameters across multiple scenarios to meet diverse requirements. And it can effectively reduce the operating temperature. This model can accelerate the process of GaN epitaxial design and provide an effective method for enhancing the performance of GaN-on-Si HEMTs.
- 23 May 2025
- Published by Springer Nature in Journal of Electronic Materials
- Vol. 54 (8) , 6802-6811
High Thermal Conductive Ga2O3 MOSFET with Diamond Substrate and its Simulation Analysis
- 23 May 2025
- Published by Springer Nature in Journal of Electronic Materials
- Vol. 54 (8) , 6802-6811
High Thermal Conductive Ga2O3 MOSFET with Diamond Substrate and its Simulation Analysis
- 30 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 73 (10) , 7457-7468
Analysis and Design of Broadband High-Efficiency Continuous Class-F/F −1 Power Amplifiers With Active Second Harmonic Injection Technique
This article presents, for the first time, the theoretical analysis and design methodology for realizing broadband high-efficiency continuous class-F/F−1 (CCF/F−1) power amplifiers (PAs) with active second harmonic injection technique. By introducing an auxiliary PA operated at the second harmonic frequency of the desired band, the optimal phase shift parameter between the drain voltage and current of the CCF/F−1 PA can be properly selected. In this way, the total drain efficiency (DE), rather than just the DE of the main PA, can be improved. That is to say, the power consumption of the auxiliary PA has been considered carefully. The calculated results show that the maximum total DEs in the CCF and CCF−1 modes are increased to 98.16% and 93.16%, respectively. At the same time, the maximum output powers are also enhanced, being 1.323 and 1.319 times larger than those in the traditional CCF and CCF−1 modes, respectively. On the other hand, the specific phase relationship between the main PA and auxiliary PA at the input node is derived. Based on the detailed design guidelines, using two GaN HEMT transistors, a proof-of-concept CCF PA with active second harmonic injection technique working across 1.1–1.65GHz (a fractional bandwidth of 40%) has been designed and fabricated. Experimental results show that the implemented PA achieves the measured output power of 41.2–42.1dBm, the total DE of 73.7%–84.9% with an average of 78.4%, and the total power-added efficiency (PAE) of 68.6%–79.1%.
- 30 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 73 (10) , 7457-7468
Analysis and Design of Broadband High-Efficiency Continuous Class-F/F −1 Power Amplifiers With Active Second Harmonic Injection Technique
This article presents, for the first time, the theoretical analysis and design methodology for realizing broadband high-efficiency continuous class-F/F−1 (CCF/F−1) power amplifiers (PAs) with active second harmonic injection technique. By introducing an auxiliary PA operated at the second harmonic frequency of the desired band, the optimal phase shift parameter between the drain voltage and current of the CCF/F−1 PA can be properly selected. In this way, the total drain efficiency (DE), rather than just the DE of the main PA, can be improved. That is to say, the power consumption of the auxiliary PA has been considered carefully. The calculated results show that the maximum total DEs in the CCF and CCF−1 modes are increased to 98.16% and 93.16%, respectively. At the same time, the maximum output powers are also enhanced, being 1.323 and 1.319 times larger than those in the traditional CCF and CCF−1 modes, respectively. On the other hand, the specific phase relationship between the main PA and auxiliary PA at the input node is derived. Based on the detailed design guidelines, using two GaN HEMT transistors, a proof-of-concept CCF PA with active second harmonic injection technique working across 1.1–1.65GHz (a fractional bandwidth of 40%) has been designed and fabricated. Experimental results show that the implemented PA achieves the measured output power of 41.2–42.1dBm, the total DE of 73.7%–84.9% with an average of 78.4%, and the total power-added efficiency (PAE) of 68.6%–79.1%.