Jia-Chuan Lin

High-performance ultraviolet (UV) photodetectors (PDs) with rapid response and high responsivity are crucial for environmental monitoring and optoelectronic applications.However, traditional N-type porous silicon (N-PSi) PDs often suffer from limited carrier separation efficiency and significant recombination losses. Here, we report an ultra-sensitive UV-PD based on a novel NP-type porous silicon (NP-PSi) thin film architecture, demonstrated for the first time. By implementing a hydrogen peroxide (H 2 O 2 )-assisted electrochemical anodization technique, a hierarchical and uniform PSi nanostructure was successfully engineered on an N-Si/P-Si layered template. The integrated NP-junction provides a robust built-in electric field that effectively facilitates the spatial separation of photogenerated electron-hole pairs while suppressing recombination. Under optimized conditions, the NP-PSibased PD exhibits a remarkable sensitivity of 67808.33%, which is approximately 28-fold higher than that of conventional N-PSi counterparts. Furthermore, the device achieves a superior responsivity of 38.60 A/W and an ultra-fast response time (rise/fall times of 0.03 s).These results underscore the synergistic effect of built-in field assistance and refined nanostructured engineering, offering a promising strategy for developing next-generation, high-gain silicon-based UV sensing technologies.

This study presents a Si-VLSI -compatible method by inserting a graphene layer between the electrode and insulation layer to efficiently mitigate the deterioration of the GHz characteristics. The nanopores on the surface of porous silicon typically hinder dense contact with metal electrode layers, causing obvious degradation in GHz operation. The graphene is embedded at the interfaces between the insulating material and the conducting electrodes, where its conductive and low-dimensional properties effectively enhance electron accumulation and release during the AC transport response. To increase specific surface area, a grooved design is engraved on the surface of the Si wafer using a high-power laser prior to the formation of porous silicon. The results demonstrate that the grooved design and the filling of graphene effectively mitigate the capacitance degradation beyond 1.25 GHz while significantly enhancing the capacitance per unit area, reaching 4.85 pF cm⁻² as measured at 3 GHz.

A $K$ -band frequency mixing divider scheme includes a downconverter double-balanced mixer and a divide-by-3 injection-locked frequency divider implemented with a TSMC 180-nm CMOS process is proposed in this letter. The compact structure is suitable for low-phase noise translation loop frequency synthesizers. Based on an inductive degeneration topology, the proposed mixer achieves a voltage conversion gain (CG) of 9.1 dB and a noise figure of 8.7 dB at 25 GHz radio frequency (RF) frequency. The measured locking range of the proposed circuit is from 8 to 8.5 GHz when the RF input signal varies from 21.5 to 25.5 GHz. The locking phase noise of injection frequency divider (ILFD) at a 100-kHz offset frequency was $-$ 117.4 dBc/Hz, while the injection signal had a phase noise of $-$ 108.3 dBc/Hz. The whole chip size, including the on-wafer pads, is 1.2 $\times$ 0.986 mm $^{2}$ .

High Electron Mobility Transistors (HEMTs) are widely recognized for their exceptional performance in high-frequency applications, yet improvements are still needed in areas of low power consumption and high efficiency. To enhance overall performance, this paper proposes a novel structure, integrating a thin AlGaN cap layer between the p-GaN and the gate metal within a developed stepped hybrid buffer layer HEMT. Observations of the electric field distribution in TCAD simulations further confirmed the formation of a dual junction. The advantages of this structure include an increased overall device performance, featuring a threshold voltage of 2.3V, a gate current of only 4.810-7 A/mm, an output current of 0.25 A/mm, a BFOM value reaching 1.48 GW/cm2, and a breakdown voltage is 1454V. These characteristics hold potential for emerging applications such as 5G communications and electric vehicle power control systems. The results of this study not only help deepen the understanding of the impact of the AlGaN cap layer on HEMT performance but also provide new ideas and directions for the design and optimization of future.

The design of a 5 GHz phase-locked loop (PLL) with a phase-adjusting function is presented. The voltage-controlled delay line (VCDL) is proposed to adjust the feedback signal phase by an externally controlled voltage. The output phase difference of multi-PLLs can be shifted from 0 $^{\circ}$ to 98.6 $^{\circ}$ , when the propagation delay of VCDL is 0.41 and 4.75 ns, respectively. The proposed PLL was fabricated in TSMC 0.18- $\mu $ m CMOS process and supplied at 1.8 V with a power dissipation of 16.38 mW. The locking time is less than 2 $\mu $ s under the different controlled-voltage ranges of VCDL.

A high-sensitivity double-roughness-structure (DRS) and its innovative manufacturing processes are originally proposed for the improvement on the sensing of the non-reactive molecule. The nitrogen molecules are served as the non-reactive test target in the study. In the DRS, the high roughness graphene is embedded into/onto the roughness surface of the porous silicon, and such the porous silicon is specially made by the “bottom-hole assisted approach” to get high-quality films. It is proved that the DRS reveals the double reinforcement on the improvement of the sensitivity based on the high surface-to-volume ratio in the sensing on non-reactive molecules.

A high-sensitivity porous silicon (PS) powder-based capacitive UV-sensor is developed on the PS-film structure. To the best of our knowledge, this is the first report on PS powder-based capacitive UV-sensors. An anodization etching approach based on a sawtooth waveform electrolytic voltage is adopted to get sufficient PS-powders. The collected PS-powders are embedded on the PS-film and covered with epoxy to improve the UV sensitivity. The results show that the increase of UV sensitivity on capacitive characteristics is almost linearly related to the PS powder mass embedded inside. The proposed method is suitable for fine-tuning and improving the equivalent permittivity of the capacitive UV-sensor without changing the device geometry design, which can be compatibly applied to Si-VLSI technology.

Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nm Al ₂ O ₃ interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability $\sigma /\mu $ (standard deviation/mean) of any resistance state was 28.7% in reset-stop voltage control methods. The multilevel switching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al ₂ O ₃ barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.

A laser direct patterning technology based on a trench method is originally proposed for porous Si device formation, which is fabricated on an n-type Si layer of a pn-diode structure. A moat-like trench designed to be a closed cylindrical surface and deep enough to reach the pn-junction separates the pn-diode into an inner part and an outer part. The experimental results clearly show that the patterned porous Si devices can be performed precisely on the inner/outer part only. No mask, deposition, light source and photolithography process are required during the electrolytic etching. In the study, the evidence of direct patterning of porous Si device at desired areas and its related distinct porosity structures are verified by scanning electron microscope and UV photoluminescence photos.