Shirshendu Das

Spin Transfer Torque RAM (STT-RAM) based Last Level Cache (LLC) offers significant benefits like high density and low refresh energy, but faces challenges like high write latency and limited endurance. Malicious attacks in a multi-core setup need access to only a single core to perform repeated attacks on specific memory locations that can lead to an accelerated lifetime degradation of the STT-RAM LLC cells. To highlight this vulnerability of STT-RAM LLC we propose two variations of TENDRA (Targeted Endurance Attack), namely, Recurring Location Attack (RLA) and Recurring Toggle Attack (RTA). Our work highlights the efficiency of these attacks on modern counter based wear leveling techniques and also the effect of wear leveling on these attacks.

Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this article, we propose Restricted Static Pseudo-Partitioning (RSPP), an effective partition-based mitigation mechanism that restricts the cache access of only the adversaries involved in the attack. It has an insignificant impact of only 1% in performance, as the benign processes have access to the full cache and restrictions are limited only to the suspicious processes and cache sets. It can be implemented with a maximum storage overhead of 1.45% of the total Last-Level Cache (LLC) size. This article presents three variations of the proposed attack mitigation mechanism: RSPP, simplified-RSPP (S-RSPP) and corewise-RSPP (C-RSPP) with different hardware overheads. A full system simulator is used for evaluating the performance impact of RSPP. A detailed experimental analysis with different LLC and attack parameters is also discussed. RSPP is also compared with the existing defense mechanisms effective against cross-core covert channel attacks.

Modern Chipmultiprocessors (CMP) use third-party intellectual properties (IP) to reduce design costs and meet deadlines. The cores in the CMP has their own private cache memories and all the cores share a common large sized Last Level Cache (LLC). All the components of CMP including cores and cache memories are connected through a Network-on-Chip (NoC). Most of the NoC components have third-party IPs. Some of these IPs may be malicious and act as Hardware Trojan (HT). In this work, we propose an HT-base attack that targets the LLC resizing techniques. The LLC resizing techniques are used to reduce the energy consumption of the LLC by shutting down unused parts of the LLC. The proposed attack can misuse the properties of these resizing techniques to reduce their energy saving up to 58%. The proposed attack can also reduce the system performance up to 18%.

In this article, the authors investigate the prospect of a new hardware trojan (HT) in Network-on-Chip (NoC) routers or network interfaces (NIs), targeting on-chip packet compression techniques.

Summary: The primary factor responsible for increasing the refresh rate is the presence of weak rows in a DRAM. They have a shorter retention time and lose charge faster than regular rows. Recently, a technique known as in‐DRAM cache was introduced in which some DRAM rows act as a separate module. The in‐DRAM cache can be used for a variety of purposes in DRAM. We present WinDRAM, an in‐DRAM cache comprised of all the DRAM's weak rows. The most recently accessed rows are copied into the in‐DRAM cache so that when the row is accessed again, both rows (original and copy) can be activated at the same time. Such simultaneous activation reduces activation time and, as a result, DRAM access latency. Dual‐row activation is the term for this concept. Because weak rows are part of the in‐DRAM cache and are frequently accessed, WinDRAM does not perform a periodic refresh on them. Existing techniques based on in‐DRAM cache do not design the in‐DRAM cache using weak rows. WinDRAM proposes a novel idea by designing the in‐DRAM cache using weak rows. Because the weak rows do not need to be refreshed, the refresh interval of the remaining rows can be increased, resulting in a refresh rate reduction of 80% to 90%. The speedup is 15% to 25% faster than standard DRAM and 12.77% faster than previous work for high memory‐intensive workloads. Overall energy consumption is also reduced by 10% to 15%.