Jaspinder Kaur

Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this article, we propose Restricted Static Pseudo-Partitioning (RSPP), an effective partition-based mitigation mechanism that restricts the cache access of only the adversaries involved in the attack. It has an insignificant impact of only 1% in performance, as the benign processes have access to the full cache and restrictions are limited only to the suspicious processes and cache sets. It can be implemented with a maximum storage overhead of 1.45% of the total Last-Level Cache (LLC) size. This article presents three variations of the proposed attack mitigation mechanism: RSPP, simplified-RSPP (S-RSPP) and corewise-RSPP (C-RSPP) with different hardware overheads. A full system simulator is used for evaluating the performance impact of RSPP. A detailed experimental analysis with different LLC and attack parameters is also discussed. RSPP is also compared with the existing defense mechanisms effective against cross-core covert channel attacks.

Prefetching is a technique used to improve system performance by bringing data or instructions in the cache before it is demanded by the core. Several prefetching techniques have been proposed, in both hardware and software, to predict the data to be prefetched with high accuracy and coverage. The memory patterns accessed by applications can be classified as either regular memory access patterns or irregular memory access patterns. Most prefetchers exclusively target either of these patterns by learning from either temporal or spatial correlation among the past data accesses observed. Our proposal focuses on covering all kinds of access patterns which can be predicted by a temporal as well as a spatial prefetcher. Running both kinds of prefetchers in parallel is not a wise design as it leads to unnecessary hardware (storage) overhead for metadata storage of temporal prefetcher. We propose broadly classifying the memory access patterns of applications on the go as regular or irregular, and then using an appropriate prefetcher to issue prefetches for the respective classes. This reduces the metadata requirement in case of temporal prefetcher by 75%. Evaluation of our proposed solution on SPEC CPU 2006 benchmarks achieve a speedup of 23.7% over the no-prefetching baseline, which is a 4% improvement over the state of the art spacial prefetcher BIP, and 13.2% improvement over the temporal prefetcher, Triage.