Raffaele De Rose

This paper proposes a reconfigurable PUF bitcell based on a multi-flavor thirteen-transistor (13T) sub-threshold voltage divider as core block, interfaced with a conversion circuit for output bit generation. The reconfigurability dramatically improves the PUF stability reducing the chance of having unstable cells, while the multi-flavor approach allows for better area efficiency. The conversion circuit also generates two auxiliary voltages exploited for soft dark bit detection. In particular, a soft calibration (SC) scheme detects and corrects the unstable cells by XORing such voltages at low supply voltage (i.e., 0.4 V) and at one or more temperature points. Moreover, a hard calibration (HC) scheme is employed along with a remapping process to further enhance the PUF stability. Raw measurements in 65-nm CMOS technology show a bit error rate (BER) of 0.13% at golden key (GK) conditions (i.e., 1.0 V and 25 °C). After implementing the proposed calibration schemes (i.e., 5-point SC or HC) along with temporal majority voting (TMV), no instability at GK conditions as well as a strong BER reduction under voltage and temperature (VT) variations were achieved. Then, zero-BER under any VT condition was observed by implementing the HC scheme along with remapping and TMV. This is obtained with an area per bit of 17,042 F², and an energy per bit of 80 fJ at a throughput of 4 Mbps.

This paper explores the instability of threshold voltage (V_TH) and dielectric breakdown in flexible n-type thin-film transistors (TFTs) featuring a bottom-gate Ti/Al₂O₃/IGZO structure. Measurements were performed in dark conditions at 25°C on a set of devices with the same channel width (W = 280 μm) and different channel lengths (L) ranging from 100 μm down to 5 μm. Regarding the V_TH instability, both hysteresis (applying V_GS from -1 V to 5 V and vice versa) and positive gate bias stress (applying V_GS = 5 V for 1000 s) data show a positive V_TH shift (ΔV_TH) ascribed to electron trapping at the channel/oxide interface or within the bulk oxide. Our study also demonstrates that in some devices the stress-induced ΔV_TH is fully recovered by applying a V_GS = -2 V for 1000 s as a result of releasing charges previously trapped during stress. Moreover, measurements highlight an increasing trend of both hysteresis- and stress-induced ΔV_TH for shorter channel devices. Consistently, time-dependent dielectric breakdown data (applying V_G = 11 V) indicate a faster process in smaller devices. Then, overall results show lower reliability in more scaled devices, thus proving that a key challenge for the investigated technology is to realize reliable short-channel TFTs.

Physically unclonable functions (PUFs) represent emerging cryptographic primitives that exploit the uncertainty of the CMOS manufacturing process as an entropy source for generating unique, random and stable keys. These devices can be potentially used in a wide variety of applications ranging from secret key generation, anti-counterfeiting, and low-cost authentications to advanced protocols such as oblivious transfer and key exchange. Unfortunately, guaranteeing adequate PUF stability is still challenging, thus often requiring post-silicon stability enhancement techniques. The latter help to contrast the raw sensitivity to on-chip noise and variations in the environmental conditions (i.e., voltage and temperature variations), but their area and energy costs are not always feasible for IoT devices that operate with constrained budgets. This pushes the demand for ever more stable, area- and energy-efficient solutions at design time. This review aims to provide an overview of several weak PUF solutions implemented in CMOS technology, discussing their performance and suitability for being employed in security applications.

This paper explores a class of highly stable static monostable physically unclonable functions (PUFs) based on stacked sub-threshold voltage dividers between two nominally identical sub-circuits as bitcell core block. More specifically, compared to our previous works where two-transistor (2T) and four-transistor (4T) voltage divider based PUFs were presented and analyzed, here we propose two novel topological variants based on six-transistor (6T) and eight-transistor (8T) solutions which arise from adopting a proper reverse gate-biasing strategy within the stack with the aim of improving the resilience to on-chip noise and voltage variations, while keeping the area overhead low. These novel solutions, along with those already proposed, were tested in 180-nm CMOS technology. Raw measurements show a nominal (at 1.8 V and 25 $^{\circ}$ C) bit error rate (BER) of 0.15% and 0.08% for the 6T-and 8T-based solutions, respectively, along with a BER variation of 0.016% and 0.002% per 0.1 V. With the implementation of a simple masking technique based on measurements at low supply voltage ( $V_{DD}$ $=$ 0.3 V at 25 $^{\circ}$ C) along with a temporal majority voting (TMV) scheme, a BER of 0.006% and lower than 9.77 $\times$ $10^{-5}$ %, which is the minimum observable BER for the adopted statistical set, was observed for the 6T-, and 8T-core based implementations, respectively, with a corresponding masking ratio of 8.71% and 7.59%. This is achieved with an area per bit of 5,174 $F^2$ (6T solution) and 6,994 $F^2$ (8T solution).

Smart tags are compact electronic devices affixed to or embedded into objects to facilitate identification, monitoring, and data exchange. Consequently, secure authentication of these tags is a crucial issue, as objects must reliably verify their identity before sharing sensitive information with other entities. The application of Physical Unclonable Functions (PUF) as a device's “digital fingerprint” has attracted significant attention, yet existing PUF-based authentication methods exhibit security vulnerabilities, either due to the authentication protocol itself or the limited reliability of the PUF technology used. Moreover, there has been a considerable focus on the software aspect, often overlooking the critical role of hardware design, which can become a target for attacks aimed at compromising the device's identity or act as a hindrance in the manufacturing process. In light of these points, this paper introduces an identification tag architecture that leverages PUF technology, focusing on authentication. This architecture features a straightforward but efficient authentication protocol, underpinned by a new and highly stable PUF model. The overall architecture encompasses particular hardware implementation aspects that significantly simplify the tag's enrollment phase and minimize vulnerabilities to attacks. The paper also describes a prototype of this identification tag and provide detailed insights into its application.

This paper introduces SIMPLY+, an advanced Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM)-based Logic-in-Memory (LIM) architecture that evolves from the previously proposed smart material implication (SIMPLY) logic scheme. More specifically, the latter is enhanced by incorporating additional circuitry to enhance the reliability of preliminary read operations. In this study, the proposed architecture is benchmarked against its conventional counterpart. Obtained results show a significant improvement in terms of reliability, i.e., the nominal read margin (RM) by a factor of ~3-4× and accordingly the bit error rate (BER) by more than four orders of magnitude. These improvements come at minimal cost in terms of circuit area and complexity compared to the conventional SIMPLY design. Overall, this research establishes SIMPLY+ as a promising solution for the design of reliable and energy-efficient in-memory computing architectures.

We design a spintronic physical unclonable function (PUF) based on sub-100 nm voltage-controlled magnetic anisotropy hybrid magnetic tunnel junctions (VCMA-MTJs). This complementary metal-oxide-semiconductor VCMA-MTJ (CMOS/VCMA-MTJ) PUF architecture was evaluated by combining micromagnetic simulations, Verilog-A modeling, and circuit-level simulations. The PUF architecture, comprising four 16 rows × 16 columns arrays, demonstrates effective read and write operations using conventional voltage sensing that are orders of magnitudes lower than previous spintronic-based PUFs. This study proves the potential of the proposed solution in security applications based on hardware authentication.

This paper introduces a voltage reference design able to operate over the wide supply voltage range from 1.8 V down to 0.2 V, and pW power. To mitigate the effect of global variations (e.g., die-to-die, wafer-to-wafer), the proposed NMOS-only architecture introduces process sensor-driven selection/merging of circuit replicas at boot (or run) time. Being the circuit replicas optimized for different process corners, their selection or merging fundamentally relaxes the traditionally conflicting design tradeoffs that affect the overall voltage accuracy in deep sub-threshold, while not requiring any testing-time trimming or non-volatile memory process option for low-cost applications. Measurements of a 180-nm test chip across 45 dice from different corner wafers demonstrate reliable operation down to 0.2 V with 3.9-pW power consumption at room temperature. The proposed process sensor-driven replica selection is shown to enable 1.6% V_REF process sensitivity (i.e., σ/μ), 34.9-μV/°C (819-ppm/°C) mean temperature coefficient, and 60.7-μV/V (0.14-%/V) mean line sensitivity across process corners. The resulting 1.4-mV overall absolute accuracy of the reference voltage across dice and corner wafers (1-σ), voltage fluctuations (0.3 V) and temperature deviation (20 °C) is improved by 1.9× compared to the case without replica selection, and by 3-15.4× compared to prior references with sub-nW consumption.