Halid Mulaosmanovic

Understanding charge trapping mechanisms and characterizing oxide traps in hafnium oxide (HfO ${}_{{2}}\text {)}$ -based ferroelectric field-effect transistors (FeFETs) is essential for addressing long read-after-write (RAW) delays and limited endurance, two key challenges hindering their adoption. In this work, we employ random telegraph noise (RTN) measurements under varying programming and polarization conditions to investigate their impact on charge trapping. We find that introducing a preliminary negative (erase) gate voltage pulse before a positive (program) pulse significantly alters the observed RTN signal, suggesting that distinct trap energies or spatial locations are activated following erase. By contrast, RTN after a positive-only program pulse exhibits highly repeatable behavior. Analysis of capture and emission time constants enables the extraction of trap energies, consistent with previously reported values in similar devices. Finally, we discuss the inherent limitations of RTN for comprehensive trap characterization. These insights advance the understanding of defect behavior in FeFETs and their role in device reliability.

Threshold voltage variability is a key concern in ferroelectric field effect transistor (FeFET) technology. In this work, a study spanning experiments, modeling, and SPICE simulations is conducted to evaluate the impact of localized FE/ dielectric (DE) distributions on the threshold voltage ( ${V}_{\text {TH}}$ ) of FeFET. The device characterization is performed on the 28-nm FeFET foundry platform. The experimental study on device-to-device (D2D) and cycle-to-cycle (C2C) variations reveals that the FeFET can be an asymmetric device, with the VTH showing dependence on the direction of current flow, as well as the magnitude of applied drain voltage ( ${V}_{\text {DS}}$ ) to the device. The TCAD modeling study reveals that the cause of asymmetry is the spatial localization of DE phases that may occur due to the random nature of the distribution. SPICE simulation for two-FeFET-based ternary content-addressable memory (TCAM) reveals that as few as two devices exhibiting the localization-induced threshold voltage shift can lead to a 64-bit search failure. Various strategies are investigated to minimize the impact of such localized phase distribution-induced threshold voltage shift (LPTS) effect. Notably, the capacitive readout of FeFET and the insertion of a floating metal electrode in the gate-stack improve the robustness.

Ferroelectric-based capacitive crossbar arrays have been proposed for energy-efficient in-memory computing in the charge domain. They combat the challenges like sneak paths and high static power faced by resistive crossbar arrays but are susceptible to thermal noise limiting the effective number of bits (ENOBs) for the weighted sum. A direct way to reduce this thermal noise is by lowering the temperature, as thermal noise is proportional to temperature. In this work, we first characterize the nonvolatile capacitors (nvCAPs) on a foundry 28-nm platform at cryogenic temperatures to evaluate the memory window (MW), on state retention as a function of temperature down to 77 K, and then use the calibrated device models to simulate the capacitive crossbar arrays in SPICE at lower temperatures to demonstrate higher ENOB (~5 bits) for $128\times 128$ multiply-and-accumulate (MAC) operations.

Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated and reconfigurable TD-nvIMC macro, fabricated in 28 nm CMOS, that combines a ferroelectric FET (FeFET)-based content-addressable memory array, a cascaded delay element chain, and a time-to-digital converter. The architecture supports binary multiply-and-accumulate (MAC) operations using XOR- and AND-based matching, as well as in-memory Boolean logic and arithmetic functions. Sub-nanosecond MAC resolution is achieved through experimentally demonstrated 550 ps delay steps, representing a $2000\times $ improvement over prior FeFET TD-nvIMC work, enabled by multilevel-state calibration with $\leq 100$ ps resolution. Write-disturb resilience is ensured via isolated triple-well bulks. The proposed macro achieves a measured throughput of 222.2 MOPS/cell and energy efficiency of 1887TOPS/W at 0.85 V, establishing a viable path toward scalable, energy-efficient TD-nvIMC accelerators.

Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.

The growing demand on new computer architectures, particularly in applications such as in-memory computing, may necessitate embedded non-volatile memories. Ferroelectric field-effect transistors offer both n-type and p-type functionality based on conventional CMOS technology. However, the issue of carrier (de)trapping, which shifts the threshold voltage shortly after the write operation, remains a challenge for applications requiring high frequency or fast access. Therefore, further understanding of the mechanism of the (de)trapping process is necessary to enhance their feasibility. While the superior room-temperature performance of p-type Si FeFETs is known, the underlying mechanisms of the detrapping process remain unclear. In this study, we perform the first systematic investigation of the (de)trapping behavior across a wide temperature range. We reveal a classic thermally-activated detrapping in n-FeFETs, extracting activation energies of 0.208 eV and 0.288 eV for Si and SiGe channels, respectively. More importantly, we uncover an anomalous, non-monotonic temperature dependence in p-FeFETs, suggesting a more complex mechanism beyond simple thermal emission. These findings provide critical insights into the physical origins of the detrapping process.

In this article, the impact of the measurement delay and connection to the body contact on the reliability of the ferroelectric field effect transistor (FeFET) under the capacitive nondestructive read mode is studied. Specifically, the endurance characteristics of the FeFET’s gate-to-source/drain capacitance are analyzed. The study is performed on 28-nm bulk Si FeFET technology, with body contact either grounded or floating. We find that the FeFET device exhibits an erase after program delay, where as the number of pulses during the bipolar stress increases, the ferroelectric switching of the FeFET reduces. During the memory window (MW) evaluation (after the bipolar stress), the system setup delays are longer than the erase after program delay in the actual operation. Hence, the ferroelectric switching is restored showing a full MW. The results indicate that the presence of this erase after program delay imposes a minimum stress frequency on the device, which in turn increases the measurement time. Furthermore, the result points toward the need to re-evaluate the standard endurance measurement practice.

In this letter, a ferroelectric field effect transistor (FeFET)-based charge-domain ternary content addressable memory (TCAM) is experimentally demonstrated for in-memory search. Specifically, foundry based FeFETs are configured in non-volatile capacitor (nvCAP) mode for charge-domain computation. A single TCAM cell consisting of 2 nvCAPs (i.e. two FeFETs) is used to perform the Store: bit ‘0’, ‘1’, ‘X’ and Search: bit ‘0’, ‘1’, ‘X’ operations. Further, SPICE simulations are performed to evaluate the feasibility of a scaled nvCAP device in a large TCAM array. The low CON/COFF ratio of a scaled device can lead to false-positive matchings, which can be countered by introducing a dummy column and input dependent charge cancellation. Finally, the charge-domain nvCAP TCAM is benchmarked against other proposed candidates, showing a ~1.5× improvement in energy efficiency over FeFET based current domain TCAM, and a ~3.3× improvement compared to resistive random access memory (RRAM) based TCAM.

In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-V_TH (HVT) state and the screening of the applied field by the channel at the low-V_TH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.