Alessandro Sottocornola Spinelli

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells.

In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D nand Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.

In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D nand Flash memories with polysilicon channel. In Part I we focus on threshold voltage (VT) fluctuations induced by traps and show that lower values for the average and rms VT arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.

In this letter, through experimental evidence collected at room temperature and in the deep-cryogenic regime, we demonstrate that the so-called vertical charge loss from the gate stack of 3-D charge-trap NAND Flash memories is a process featuring widely distributed time constants. Results reveal that the turn-on of these time constants depends on the temperature at which the program operation is carried out. This, combined with the dependence of the time constants on the temperature at which vertical charge loss is monitored, gives rise to an apparent activation energy of the cell threshold-voltage transient during data retention that is close to zero when data retention and program occur at the same temperature. This phenomenology must be carefully taken into account when trying to extend the working temperature of NAND Flash memories down to the deep-cryogenic regime.

We report experimental evidence revealing a nonmonotonic temperature dependence of Time-Dependent Dielectric Breakdown (TDDB) in galvanic isolators based on polymeric dielectrics. In particular, the lifetime of the device under TDDB stress decreases when temperature rises from room temperature to 100°C and then steeply increases above the latter temperature. This effect, which introduces a turnaround in the Arrhenius plot of device lifetime, is explained as a result of two competing processes leading to the strengthening and weakening of polymeric chains in the dielectric material, respectively. The proposed physical picture is further supported by a simple numerical model that allows to investigate the temperature dependence of TDDB in galvanic isolators based on polymeric dielectrics under various working conditions.