Anne-Johan Annema

This paper describes a CMOS frequency reference system that achieves quartz-crystal-oscillator-rivaling frequency accuracy and power consumption across a temperature range of 228∘, with low degradation over lifetime. This system uses only a batch calibration and a sample-specific single-temperature production-time calibration. The reference frequency is generated by a tunable RC-based oscillator (RCO) at relatively low power. The RCO’s significant process and temperature dependencies, and degradation over lifetime, are eliminated by periodically recalibrating it to a co-integrated inherently robust LC-oscillator (LCO). The resulting hybrid RC/LC CMOS frequency reference system combines the low-power properties of the RCO and the single-trim highly-accurate and low-ageing properties of an LCO. This paper reviews circuit and system aspects of this frequency reference system, complemented with measurement results and insights for key devices and for many effects that limit system accuracy over wide temperature ranges and over lifetime.

We present electrical and optical (λ = 850nm) measurement results of back-gate controlled SOI PIN-diodes without a front-gate, with an intrinsic Si film thickness of only !+6nm. These ultrathin-body PIN-diodes were fabricated as exploratory devices in a commercially available Fully-Depleted Silicon-On-Insulator (FDSOI) technology, without requiring additional process steps.We show that electrostatic back-gate tuning significantly affects the electrical characteristics and optical responsivity (Ro). This leads to a novel method to extract the optimal back-gate bias for maximum Ro from electrical measurements. The maximal measured Ro at 0V bias across the diode and with optimal back-gate bias equals 62 μ A/W, with a.3dB bandwidth of 5.9GHz, and a.6dB bandwidth of 15GHz. These PIN-diodes potentially open the way to new (THz) circuits, sensors, novel/complementary process control monitoring structures, and optical applications. They also enable interaction between the hybrid (bulk) and SOI devices, which is a unique feature of FDSOI technologies.

Inductors with both a high quality factor and a low temperature coefficient of inductance are crucial for highly stable, fully integrated frequency references. We present tapered multipath inductors in a standard CMOS technology that achieve $\QL$ $>$ 8 and $\TCL$ $=$ 1 ppm/ $^\circ$ C in aluminum-based (Al) top metal and reach $\QL$ $>$ 19 with a $\TCL$ $=$ 30 ppm/ $^\circ$ C in a thick copper-based (Cu) metal layer, both at 2 GHz.

This article presents a frequency reference system that combines high frequency accuracy and low power consumption using a single-point temperature trim and batch calibration. The system is intended as a low-cost fully integrated crystal oscillator replacement. In this system, the oscillation frequency of a power-efficient, but process, voltage, temperature (PVT) and lifetime (L)-sensitive current-controlled ring oscillator (CCO) is periodically (re)calibrated by the well-behaved frequency stability of an untuned LC –based Colpitts oscillator (LCO), which is optimized for stability over PVT variations and lifetime (PVTL). During the single-point room temperature factory trim, the frequency of the LCO is determined and the result is digitally stored. An on-chip calibration engine tunes the CCO to the target frequency based on the LCO frequency, temperature sensor information, and digitally stored trimming information, thus effectively improving the frequency stability of the ring oscillator. The relatively high-power LCO is heavily duty-cycled to minimize the overall power consumption. A prototype fabricated in a 0.13- $\mu$ m CMOS SOI process and assembled in a plastic package demonstrates an inaccuracy lower than $\pm$ 93 ppm over a temperature range from $-$ 63 $^{\circ}$ C to 165 $^\circ$ C across samples. The presented frequency reference system, including on-chip voltage regulators and a temperature sensor, occupies a chip area of 0.69 mm $^2$ and consumes about 64 $\mu$ A from a single 3.3-V supply. The frequency error due to supply variation is roughly 92 ppm/V. The mean frequency shift due to aging, measured before and after a six-day storage bake at 175 $^\circ$ C, is only 52 ppm.

A novel algorithm is presented that can resolve frequency ambiguity that arises from sampling a set of signals spanning more than a single Nyquist zone. The method uses two samplers, each sampling the same input signal with different (non-integer multiple) sampling rates. The algorithm is able to resolve frequency ambiguity and reconstruct signals with an orthogonal frequency basis spanning multiple Nyquist zones, provided that the aggregate information-bearing bandwidth of the signals is less than half the cumulative data converter sampling rates. This manuscript describes the theoretical background for the algorithm and validates it through measurements performed on a test-board comprising of two 10 bit analog-to-digital converters clocked at two different (non-integer multiple) sample rates. Measurements show that even in the presence of aliasing, an orthogonal signal spanning multiple Nyquist zones can be fully reconstructed.

A single-trim, highly accurate Colpitts-based frequency reference is presented. Our analysis shows that the Colpitts-topology outperforms the cross-coupled LC -topology in terms of temperature stability. Measurements on prototypes in a 0.13- $\mu \text{m}$ high-voltage CMOS silicon on insulator (SOI) process were carried out from −50 °C to 170 °C. Based on sample-specific single room temperature trim and batch calibration, our frequency reference achieves an accuracy of ±120 ppm for 16 samples from a single wafer utilized for extracting the batch-calibration polynomial and ±300 ppm for 48 samples across three wafers from the same batch. This is a 4 $\times $ improvement over related single-trim state-of-the-art solutions. Frequency drift due to aging, tested after a six-day 175 °C storage, is below 100 ppm. The oscillator core dissipates 3.5 mW from a 2.5-V supply and has 220-ppm/V supply sensitivity without supply regulation.

The CMOS silicon avalanche-mode light-emitting diode (AMLED) has emerged as a potential light source for monolithic optical interconnects. Earlier we presented a superjunction light-emitting diode (SJLED) that offers a higher electroluminescent intensity compared to a conventional AMLED because of its more uniform field distribution. However, for reducing power consumption low-voltage (≤15V) SJLEDs are desired, not explored before. In this work we present a TCAD simulation feasibility study of the low-voltage SJLED for various doping concentrations and device dimensions. The results show that for obtaining a constant field, approximately a tenfold more aggressive charge balance condition in the SJLED is estimated than traditionally reported. This is important for establishing a guideline to realize optimized RESURF and SJLEDs in the ever-shrinking advanced CMOS nodes.

Highly efficient switch-mode class-E power amplifiers (PAs) are sensitive to load impedance variations. For voltage standing wave ratios (VSWRs) up to 10:1, the peak switch voltage and the average switch current can increase by a factor of 1.7 and 2.5, respectively, relative to those under nominal load conditions, imposing serious reliability risks. This paper describes a technique to self-protect class-E PAs to decrease their sensitivity to load variations, relying on the tuning of the switch-tank relative-resonance frequency, implemented by an on-chip switched-capacitor bank (SCB). To validate the technique, load-pull measurements are conducted on a class-E PA implemented in a standard 65-nm CMOS technology, employing an off-chip matching network, augmented with a fully automated self-protective control loop. Under nominal conditions, the PA provides 17.8,dBm at 1.4,GHz into 50,Ω from a 1.2-V supply with 67% efficiency. The proposed self-protective PA can reduce its peak switch voltage below the technology- and switch design-related limit for any load with a VSWR up to 19:1 while not considerably impacting output power and efficiency, which see a maximum degradation of 1.6,dB and 6%, respectively. Furthermore, a class-E PA designed to safely handle 2.5x the nominal average switch current can reliably operate for VSWRs up to 19:1 when protected with our technique.

Outphasing Class-E Power Amplifiers (OEPAs) using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In this work the linearity of OEPAs using non-isolating power combiners is studied theoretically and validated by measurement of a 1.8GHz 20dBm OEPA implemented in a standard 65nm CMOS technology using an off-chip transmission-line based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, -31dB RMS EVM level and below -30dB ACLR were measured for a 13.1dBm 6.25MHz 30Mbit/s 7dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency.

Class-E RF power amplifiers (PAs) are very power efficient under nominal operating conditions. Due to incorporating two tuned tanks, the dependence on the load impedance is, however, relatively large, resulting in, e.g., load-dependent output power, power efficiency, peak voltages, and peak (and average) currents which can lead to reliability issues. This paper presents load-pull analyses for class-E RF PAs from a mathematical perspective, with analyses and discussions of the effects of the most common nonidealities of class-E PAs: the limited loaded quality factor (Qloaded) of the series filter, switch on-resistance, the limited quality factor of the dc-feed inductor, load mismatch-dependent switch conduction loss, and the limited negative voltage excursions (due to, e.g., the reverse conduction of the switch transistor for negative voltage excursions). The theoretical findings are backed up by extensive circuit simulations and load-pull measurements of a class-E PA implemented in 65-nm CMOS technology. The PA provides 18.1-dBm output power and 72% efficiency at 1.4 GHz under nominal operating condition employing an off-chip matching network.