Mark Stefan Oude Alink

Audio classification in edge devices has many applications and can be implemented at varying levels of complexity, typically consisting of a feature extractor followed by a classifier. Such devices are often always-on, constantly listening to their surroundings, and have a small form factor; therefore, they require low-power operation and high area efficiency. A passive switched-capacitor (SC)-based analog feature extractor (AFEx) is good for programmability and energy efficiency. However, it suffers from area inefficiency due to the large capacitors needed to reduce $kT/C$ noise. To address this issue, a 16-channel analog $N$ -path filterbank with an amplifier and a feedback Miller capacitor is designed, significantly reducing the physical capacitance on chip by a factor of 30 compared to not using a Miller capacitor while achieving the same noise performance, and by a factor of 8 compared to the state-of-the-art (SOTA). The same amplifier also provides gain, eliminating the need for a low-noise amplifier (LNA) at the front end. Each $N$ -path filter uses only two paths with 50% duty-cycled clocks, simplifying clock generation and reducing power consumption. Moreover, all clock frequencies are derived from only a single 32.768-kHz low-power system clock. Using the zero-IF output of the two-path filter for amplitude extraction allows filtering and mixing to be reduced into a single step. The 65-nm low-power CMOS chip consumes 475nW, comparable to other works in the literature. However, this work includes amplification and uses only 12% of the capacitance per channel of other SC-based AFExs, making it more area efficient. The total input-referred noise (IRN) is $120~{\mu }$ V_RMS, which is equivalent to a signal-to-noise ratio (SNR) of 18dB for ~1-m speaker–microphone distance. Competitive maximum classification accuracy of 87.2% for keyword spotting (KWS) is achieved, as well as a classification accuracy robustness of >70% for an input voltage range from 1 to ~260mV_RMS (~50-dB SNR range) on the Google Speech Command Dataset (GSCD) for a 12-class (ten keywords) detection using a lightweight software classifier.

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Provides society information that may include news, reviews or technical notes that should be of interest to practitioners and researchers.

This article presents a wideband resistive step RF attenuator implemented in 22-nm fully depleted silicon-on-insulator (FDSOI) CMOS technology with simultaneous second- and third-order intermodulation (IM₂ and IM₃) distortion cancellation. We propose a back-gate equalizer (BE) switch topology that converts even-order distortion into odd-order distortion, enabling simultaneous cancellation of the converted distortion and the third-order distortion at the attenuator output. This results in a highly linear and controllable attenuator. A five-step T-attenuator, including a bypass mode, is implemented, occupying 0.0066 mm². An insertion loss (IL) of 1.7 dB in bypass mode is observed for both the BE and a reference (Ref.) design. Return loss (RL) remains better than 10 dB up to 10GHz for all settings, except in bypass mode, where it is better than 10 dB up to 7GHz. The measured IIP₃ is approximately +30 dBm for both designs, while IIP₂ ranges from +60 to +80 dBm for the BE design and around +50 dBm for the Ref. design. An improvement of up to 20 dB in IM₂ is observed for the BE design compared to the Ref. design. Compared to prior work, this work also introduces a refined design strategy for IM₃ distortion cancellation and several other circuit-level optimizations. The demonstrated IIP₂ and IIP₃ performance makes the attenuator designs well-suited for today’s high-linearity RF front-ends in highly integrated systems-on-chip (SoC).

We present a Monolithically Integrated (MI) dualjunction monitoring photodiode (PD) and transimpedance amplifier (TIA). The photocurrent originates from the Deep NWell (DNW)/P-type substrate (PSUB) (< 5 GHz) and the P-Well (PW)/DNW (> 1 GHz) junctions. The presented combination of bulk PD and 22nm Fully-Depleted Silicon-On-Insulator (FDSOI) TIA (18GHz bandwidth, 17.8pA/√Hz noise level) advances the state-of-the-art in MI high-speed optical monitoring and reduces the inherent trade-off in MI solutions regarding PD (responsivity & bandwidth) and RF circuitry (ft) performance.

The ever-increasing computational load and shrinking power budget have accentuated the need for energy-efficient operation of edge devices. In this article, a combination of static CMOS logic and hybrid pass transistor logic with Static CMOS output (HPSC), which has no floating or weak nodes and is thus as robust to noise as static CMOS logic, is used for designing toolchain-compatible super- $\text {V}_{\text {th}}$ standard cells. Optimized HPSC variants of a 2/3-input XOR cell, a 2/3-input XNR cell, a half adder cell, a full adder cell, and two variants of a 1-bit multiply–accumulate combinational cell are presented in a commercial 65nm low-power CMOS technology. Measurements of test structures based on ring oscillators and dummy path techniques show an average frequency and average energy-delay product improvement of up to 30.3% and 32.5%, respectively, at typical conditions. The proposed cells’ superior performance compared to the commercially available standard cells is also highlighted in terms of propagation delay, leakage, and dynamic power consumption. This shows a promising approach for foundries or other commercial entities to improve digital design performance to about half a technology node at no additional cost.

We present electrical and optical (λ = 850nm) measurement results of back-gate controlled SOI PIN-diodes without a front-gate, with an intrinsic Si film thickness of only !+6nm. These ultrathin-body PIN-diodes were fabricated as exploratory devices in a commercially available Fully-Depleted Silicon-On-Insulator (FDSOI) technology, without requiring additional process steps.We show that electrostatic back-gate tuning significantly affects the electrical characteristics and optical responsivity (Ro). This leads to a novel method to extract the optimal back-gate bias for maximum Ro from electrical measurements. The maximal measured Ro at 0V bias across the diode and with optimal back-gate bias equals 62 μ A/W, with a.3dB bandwidth of 5.9GHz, and a.6dB bandwidth of 15GHz. These PIN-diodes potentially open the way to new (THz) circuits, sensors, novel/complementary process control monitoring structures, and optical applications. They also enable interaction between the hybrid (bulk) and SOI devices, which is a unique feature of FDSOI technologies.