Matthew O. Reese

Improved back contacts can benefit CdTe photovoltaics (PV). In this work, Cd(Se,Te) PV absorbers are cooled during Au evaporation to thermally quench a chemical reaction occurring between gold and CdTe and the generation of a reaction product that lowers device efficiency. Reducing substrate temperature enhances PV power conversion efficiency via open‐circuit voltage and fill factor increases. X‐ray photoelectron spectroscopy (XPS) reveals that lower temperature also reduces chemical perturbations of the CdTe, potentially linking back contact formation to a CdTe degradation product that hinders PV performance. Comparing reaction enthalpy and substrate heating energy shows that back contact formation by sputtering elemental metals onto ZnTe may exhibit a degradation pathway analogous to that of CdTe/Au reported here. Degradation‐diminishing contact formation processes are therefore of general interest for optoelectronic devices, and the reduced substrate temperature in this study is one example.

Deployment of photovoltaics in space requires devices that combine high‐efficiency, low areal mass, and resilience to harsh environments. Historically, high‐efficiency multijunction III–V materials have dominated space power systems; however, their high cost and limited manufacturing throughput motivate the exploration of scalable alternatives. While CdTe‐based thin‐film photovoltaics offer an attractive option, their performance on non‐conventional substrates can suffer from front contact instability under higher‐temperature processing. Here, the role of front contact chemistry in limiting cell performance is investigated using CdTe‐based devices fabricated on 150 μm thick Ceria‐doped space‐qualified 0214 Corning glass. A matrix of four transparent conducting oxides (TCOs: CTO, AZO, ITO, IZO) combined with two n‐type emitters (MZO, IGO) reveals chemical stability at the front interface—rather than absorber composition alone—governs recombination losses, voltage deficits, and device reproducibility. Chemically stable front contact combinations suppress elemental diffusion and interfacial degradation, resulting in significantly improved carrier lifetimes and junction quality. These insights are validated through record‐certified Cd(Se,Te) cell efficiencies of 18.4% under AM1.5G and 16.2% under AM0 illumination on ultra‐thin glass. Beyond CdTe, this work provides a general framework for the rational selection of TCO/emitter interfaces in superstrate thin‐film photovoltaics, including emerging technologies like metal halide perovskites, while enabling high‐efficiency, lightweight photovoltaics for space applications.

Current encapsulation architectures for thin‐film metal halide perovskite do not adequately eliminate all ambient stressors. Here, we develop low transmission rate barrier layers using atomic layer deposited (ALD) aluminum oxide grown directly on the completed photovoltaic (PV) device stack to provide an additional seal, prior to full packaging. We investigate the effect of deposition temperature and oxidant chemistries on the barrier growth for protection of perovskite photovoltaic devices. We characterize the layers individually, then integrate into devices to detail the tradeoff between protection and deposition compatibility. To enhance compatibility and impermeability, we present an approach using water as the aluminum oxidant during nucleation and switching from water to ozone for the remainder of the growth. At 50 nm, the barrier results in a water vapor transmission rate (WVTR) of 4.5·10 ⁻⁴ g/m ² /day, and 1,000‐hour device stability under 45°C with 85% relative humidity without further packaging. This barrier provides sufficient protection to enable minimal degradation of the perovskite solar cells while completely submerged in water for 140 minutes. Additionally, we characterize the oxygen transmission rate (OTR) to be 0.49 cm ³ /m ² /day at 23°C and 0% relative humidity, which is 1.5 orders of magnitude improvement over the OTR of the current encapsulation.

To meet expected 2045 LFP deployment, impurity characterization must improve. New, sufficiently pure, and low-cost iron precursors must be identified, and total phosphorous demand could consume 22% of current phosphate rock supply for fertilizers.

Local resistance imaging can provide information on nm-scale carrier distribution in semiconductor devices. Scanning spreading resistance microscopy (SSRM), an atomic force microscopy-based nm-scale resistance mapping technique, has been developed for carrier delineation in Si microdevices. We report on the development and validation of SSRM on CdTe materials, by testing on molecular beam epitaxy (MBE) grown CdTe films. The probe/CdTe contact resistance was suppressed sufficiently below sample's spreading resistance by pressing the probe into the sample with ∼mN contact force and applying a large sample/probe forward bias voltage (Vs), which was understood by analyzing current-voltage (I-V) involving a serially connected insulating top layer with underlying spreading resistance. The carrier concentration as deduced from the resistance measurement, using a single mobility value, is consistent with Hall measurement with a standard deviation of 14% based on a set of MBE films with carrier concentrations in the range of 1015–1016/cm3. The doping polarity was readily identified by flipping Vs polarity, where the resistance with reverse Vs is orders of magnitude larger than forward Vs. While focusing on the SSRM technique validation, we also show an example on an As-doped Cd(Se,Te) polycrystalline thin film of a high-performance CdTe solar cell, which illustrates the local resistance nonuniformity with up to two orders of magnitude differences, indicating if local mobility is roughly constant, local carrier concentration can have significant nonuniformity.

Single-crystal model systems are valuable tools to investigate fundamental material properties. In this work, we use molecular beam epitaxy to deposit in situ arsenic (As) doped single-crystal CdTe films on large area Si substrates to better understand As doping for photovoltaic applications. We found that As incorporation is highly temperature dependent: a substrate temperature difference of 50 °C can lead to several orders of magnitude difference in As concentration. Cd overpressure during in situ doping may limit out-diffusion of As but decrease As incorporation, especially at lower growth temperatures. Carrier concentrations greater than 1016 cm−3 can be achieved with or without Cd overpressure when annealed at temperatures above 500 °C. However, unlike the low (∼1% to 5%) dopant activation commonly observed in polycrystalline CdTe, our films achieve significantly higher activation ratios—exceeding 50%, and in some cases approaching 80%. These values are consistent with or exceed prior reports in single-crystal CdTe systems. In addition to as-deposited arsenic concentrations, we also consider arsenic distribution after different rapid thermal processing temperatures. We propose a detailed definition and description of how arsenic incorporation is considered and calculated. Due to carrier concentration saturation, As incorporation also needs to be controlled to average levels of 1017 cm−3 to achieve high activation. These findings suggest that higher annealing temperature regimes may be beneficial to polycrystalline CdTe based PV devices.

In state-of-the art polycrystalline CdTe photovoltaics, group-V dopant activation is about 2%. Low activation can create electronic defects and lead to recombination and band tail losses. To develop methods to overcome this limitation, dopant activation was systematically investigated using molecular beam epitaxy (MBE) grown single crystal bilayers of As-doped CdTe on undoped CdTe. Results suggest multiple paths for improved As-activation in polycrystalline CdTe-based devices. It was found that the carrier concentration in this MBE material saturated at ∼3 × 1016 cm−3, with high levels (>50%) of As-activation possible. High activation could be achieved with a post-growth activation temperature of ∼450 °C, when the initial doping level was below the saturation level. However, at typical polycrystalline As incorporation levels (>5 × 1016 cm−3), the excess As is inactive or compensating, requiring elevated temperatures (500–600 °C) to achieve high activation. Oxygen in the annealing ambient was detrimental, while the effect of CdCl2 in the ambient is more case-dependent. A 575 °C activation anneal was combined with a 450 °C CdCl2 treatment to better understand the implications for polycrystalline CdTe. Interestingly, on highly doped samples, processes ending with a high temperature step displayed high activation, while those ending at 450 °C significantly reduced the carrier concentration (with or without CdCl2 in the ambient). Low activation can be restored with another high temperature anneal, allowing reproducible toggling between high and low activation based on the final temperature. Photoluminescence revealed the presence of donor–acceptor pairs in the low activation state that appear to be associated with a compensating defect.

Cd(Se,Te) photovoltaics (PV) are the most widely deployed thin-film solar technology globally, yet continued efficiency improvements are stymied by challenges at the device hole contacts. The inclusion of solution-processed oxide layers such as AlGaO_x in the contact stack has yielded improved device open-circuit voltages (V_OC) and fill factors (FF). However, contradictory mechanisms by which these layers improve the device properties have been proposed by the research community. We demonstrate in this work that an underappreciated property of such spin-coated layers is the preferential deposition at grain boundaries, a process that isolates the grain boundaries during contact metallization. The effects of grain-boundary isolation are probed by varying the coverage of solution-processed AlGaO_x "barrier" layers on the Cd(Se,Te) surface, quantified by scanning Auger microscopy. Examining coverage-dependent V_OC and FF, it was observed that isolating the grain boundaries during metallization is sufficient to prevent damage to the absorber that occurs in devices lacking a barrier layer, while additional coverage contributes to the increased series resistance. Such an effect is agnostic to the material used as a barrier layer, as long as the material does not itself damage the absorber. Spin-coated SiO_x was used in place of AlGaO_x for an equally beneficial effect. This grain-boundary isolation phenomenon is also observed during Mo deposition and in absorbers that have been contacted with a nitrogen-doped ZnTe layer. The mechanisms by which metallization may degrade the absorber are discussed, as are contact design strategies leveraging barrier layers, which may lead to improved device efficiencies.