Trio Adiono

Myocardial infarction (MI) is a leading global health concern, typically diagnosed using ECG, biomarkers, or imaging, which costly or unavailable in low-resource settings. This study presents a non-invasive, machine learning-based approach using phonocardiogram (PCG) signals for classifying normal, ST-elevation MI (STEMI), and non-ST-elevation MI (NSTEMI). The proposed approach leverages the acoustic signatures of cardiac mechanical activity, capturing subtle variations in heart sound morphology and timing associated with ischemic myocardial dysfunction. The processing pipeline included PCG acquisition via electronic stethoscope, band-pass filtering, envelope-based segmentation, feature extraction, and selection using Mutual Information and K-best ranking. We evaluated the method using a diverse dataset of 104 subjects from Indonesia and Japan to ensure generalizability across ethnic and physiological variations. Eighteen key features with mutual information values up to 0.82 bits were used to train AdaBoost and Gradient Boosting models. Without parameter tuning, these models achieved 88.30% and 93.00% accuracy, respectively. After optimization, AdaBoost reached 94.00% accuracy, and Gradient Boosting achieved 98.30% accuracy and a 95.10% F1-score. These results outperform previous bagging-based methods of 86.00% accuracy, demonstrating improved accuracy and robustness. This work highlights the potential of PCG-based MI detection as a low-cost, non-invasive diagnostic alternative, particularly valuable for early screening and triage in resource-limited healthcare settings.

This paper presents a novel hardware-software co-deisgn approach to accelerate Q-learning algorithms using a RISC-V-based System-on-Chip (SoC) design. We introduce a maze-stitching algorithm that enables efficient solving of large, complex mazes by decomposing them into smaller sub-mazes and thus can perform Q-Learning computation in low-complexity hardware accelerator. Furthermore, we provide a comprehensive analysis of the algorithm’s complexity, theoretical performance gains, and practical implementation results. The proposed implementation demonstrates significant performance improvements over traditional software approaches, achieving speedups ranging from 84× to 233× for complex maze-solving tasks while maintaining a small footprint. The algorithm, even without the accelerator also achieved speedups ranging from 13× to 36×. The proposed system combines a 64-bit RISC-V core with a Q-Learning accelerator, operating at 50MHz on an Arty A7-100T FPGA. The maze-stitching technique allows for scaling to larger problem sizes while maintaining hardware efficiency. The proposed work can be applied to a lightweight accelerator and provides a scalable solution for resource-constrained edge computing environments.

Optical wireless communication (OWC) has been considered a promising solution for overcoming the spectrum limitations of RF in wireless communication. However, studies on OWC systems, particularly on actual real-time prototyping, are limited and only focus on simulation and experiments using waveform generators and oscilloscopes. Meanwhile, the data rate requirements for optical communication systems are rapidly increasing, approaching the Gbps range. Therefore, the development of real-time prototypes with high data speeds is essential and requires super sample rates (SSR), necessitating signal processing blocks capable of processing multiple samples in parallel within a single clock cycle while operating at very high clock frequencies. To address these requirements, this work proposes a parallel implementation of an orthogonal frequency division multiplexing (OFDM) baseband processor on an FPGA for OWC systems. The proposed system operates with a bandwidth of 320 MHz, achieving a maximum raw data rate of 720 Mbps at 16-QAM 3/4 modulation. This performance is comparable to that of the IEEE 802.11be WiFi 7 standard. The proposed system is applicable not only to underwater OWC but also for indoor OWC (e.g. Li-Fi), broadening its potential use cases in next-generation wireless communication networks.

In recent years, the development of artificial intelligence (AI) in aquaculture technologies has reached an unimaginable level of complexity with vast variations. One of the AI applications in aquaculture is smart fish appetite detection using convolutional neural networks (CNNs). This article specifically discusses the hardware implementation of the R(2+1)D CNN model, a variety of CNN that deconstructs 3-D convolutions into separate spatial (2-D) and temporal (1-D) components, achieving a balance between computational efficiency and accuracy. In this article, we provide several ideas and insights for the R(2+1)D model hardware implementation, highlighting its design complexity, performance, and potential applications in multimodal deep learning architectures by using the Winograd domain convolution. We also implement the R(2+1)D cores in parallel two and four. Experimental results show that the parallel four cores achieve up to 112.29× and 183.37× faster speed than the reference Tensorflow program for the 1-D and 2-D CNNs, respectively. The proposed parallel R(2+1)D CNN cores are implemented using the PYNQ FPGA board. The work is useful for embedded systems, FPGA implementations, and application-specific IC applications in aquaculture.

Reinforcement Learning (RL) applications are rapidly expanding across various fields, including robotics, autonomous vehicles, drones, communication systems, and control. However, RL computations are inherently complex and resource-intensive due to dynamic state spaces and real-time processing demands. This paper proposes a novel RL accelerator hardware architecture for edge computing, capable of supporting both inference and training modes. The design, tailored for Deep Q-Network (DQN) with Q-values computed using an Artificial Neural Network (ANN), employs hardware sharing and approximate activation functions and multipliers to enhance efficiency. Shared processing modules minimize chip size and power consumption, achieving an area efficiency of 44.25 KIPS/1KLUTs and 14.65 KIPS/1KLUTs. Implementation results demonstrate state processing times of 1.43 μs for inference and 4.31 μs for training. Deployed on an Ultra96 FPGA at 70 MHz, the system delivers 671× and 287× speedups for inference and training, respectively, with a DQN accelerator power consumption of just 13 mW. This architecture is highly suitable for autonomous systems in edge computing environments, addressing resource limitations and enhancing computational efficiency.

The variation in the k-factor value significantly influences the performance of unmanned aerial vehicle (UAV) air-to-ground point-to-point line of sight (A2G PTP LOS) communications over a Rician channel at 1,800 MHz using quadrature phase shift keying (QPSK) modulation and orthogonal frequency division multiplexing (OFDM) techniques. The research emphasizes the impact of the k-factor, which quantifies the dominance of the line-of-sight component over multipath scattering. The variation in the k-factor significantly influences UAV A2G PTP LOS communication performance for the empirical model (EM), as it involves precise measurements of the received power level in dBm from UAV to ground control station (GCS) across varying distances and altitudes. We introduce a method to compute the k-factor by assessing the ratio of the line-of-sight signal power to the multipath signal power, thereby enhancing channel modeling accuracy. Empirical analysis shows a strong correlation between bit error rate (BER) and signal-to-noise ratio (SNR) with differing k-factor values; a higher k-factor of 16.3 markedly improves performance, virtually eliminating errors at a 10 dB SNR, while a lower k-factor of 2.39 still shows significant errors at a 30 dB SNR. These results highlight the necessity of optimizing the k-factor in UAV A2G PTP LOS systems to ensure stable and reliable communication under diverse operational conditions.