Eduardo Peralias

This paper introduces a novel, non-invasive, and ultra-fast experimental procedure for the characterization of electrostatic energy harvesters. The method builds on a new analytical solution derived from a piecewise expansion of the generator’s effective time-varying capacitance. The formulation is general and applies to both electret-based and electret-free electrostatic nanogenerators (ENGs), providing a unified inter­pretation of their voltage and charge dynamics. Unlike the standard power output characterization, which typically relies on diodes and active circuitry that inevitably load and perturb the harvester and require long data acquisitions under periodic excitation to ensure convergence, our method extracts the intrinsic properties of the device from a short measurement of a single ENG event. The test setup is extremely simple, re­­qui­­ring only an oscilloscope and no external excitation source. This fast and non-invasive operation is particularly relevant in the current trend of device miniaturization, where ENGs become smaller and the parasitic contributions of the measurement setup grow comparable to the contribution of the device. The methodology has been validated through detailed elec­trical simulations and experimental evaluation on different triboelectric nanogenerators (TENGs) for water droplet energy harvesting applications (WD-TENGs), demonstrating accurate parameter extraction and reliable performance predictions. The accompanying characterization tool C-ENGiNE was used to automate and reproduce the full workflow during validation.

As nascent nonlinear oscillators, nano-constriction spin Hall nano-oscillators (SHNOs) represent a promising potential for integration into more complicated systems such as neural networks, magnetic field sensors, and radio frequency (RF) signal classification. Their tunable high-frequency operating regime, easy synchronization, and CMOS compatibility can streamline the process. To implement SHNOs in any of these networks, the electrical features of a single device are needed before designing the signal detection CMOS circuitry. This study centers on presenting an empirical electrical model of the SHNO based on a comprehensive characterization of the output impedance of a single SHNO and its available output power in the range of 2–10 GHz at various bias currents.

This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming $LC$ package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.

Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 µV even for an impedance as large as 300 Ω and a noise figure of 5.3 dB_{300 Ω}. A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs.

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude.

This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic-basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.