Adoracion Rueda

This paper presents a digital nonlinearity calibration technique for ADCs with strong input-output discontinuities between adjacent codes, such as pipeline, algorithmic, and SAR ADCs with redundancy. In this kind of converter, the ADC transfer function often involves multivalued regions, where conventional integral-nonlinearity (INL)-based calibration methods tend to miscalibrate, negatively affecting the ADC's performance. As a solution to this problem, this paper proposes a novel INL-based calibration which incorporates information from the ADC's internal signals to provide a robust estimation of static nonlinear errors for multivalued ADCs. The method is fully generalizable and can be applied to any existing design as long as there is access to internal digital signals. In pipeline or subranging ADCs, this implies access to partial subcodes before digital correction; for algorithmic or SAR ADCs, conversion bit/bits per cycle are used. As a proof-of-concept demonstrator, the experimental results for a 1.2 V 23 mW 130 nm-CMOS pipeline ADC with a SINAD of 58.4 dBc (in nominal conditions without calibration) is considered. In a stressed situation with 0.95 V of supply, the ADC has SINAD values of 47.8 dBc and 56.1 dBc, respectively, before and after calibration (total power consumption, including the calibration logic, being 15.4 mW).

A technique for real-time monitoring of bio-impedances using a Voltage Oscillation (VO) methodology is proposed. The main idea relies on connecting the bio-system in such a way that a suitable electrical oscillator, which only uses a DC power source, is built. Thanks to the employed electrical models, the oscillation parameters can be directly related to the biological test. System simulations show that the impedance values of a tissue, called herein Z _x , can be determined by measuring the actual frequency and amplitude of the proposed VO system, being possible to select the frequency range to optimize the system sensitivity.

This paper presents the implementation of a compact R-2R Digital-to-Analog Converter (DAC) for BIST applications of analog and mixed-signal circuits. It focuses on evaluating the DAC design requirements and its possibilities in structural and alternate test methodologies. More concretely, the aim of the paper is the low-cost generation of digitally programmable DC voltages for parametric deviation injection. For the sake of validation, these voltages will be considered to modify the voltage references of bias circuit or cascode voltages in op-amps. The DAC has been implemented in a UMC 65nm LL CMOS process, and comprises a front-end passive R-2R ladder followed by an active buffer based on a two-stage amplifier with Miller's compensation. Special care has been taken in the resistors ladder layout, as a critical parameter to minimize the mismatch impact due to process variations and maximize the final static behavior. The total power consumption and overall die area for the R-2R DAC ladder are 120μW and 88x64μm2, respectively. The op-amp design could be optimized depending on the load and driving requirements.

This paper presents the design of an efficient buffering solution for BIST applications for static linearity test in high-speed high-performance ADCs. Relevant design trade-offs for buffer reusability are studied in a nanometric CMOS technology. The circuit is devised to isolate the on-chip generator output from the high-frequency switching noise at the sampling input of the ADC under test. This buffering stage, often overlooked in the literature, is in fact an essential building block for the correct functionality of the BIST in high-speed high-performance applications. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 2.5V 65nm CMOS process is presented here as demonstrator. Transistor-level simulations with a 2Vpp sinusoidal test-stimulus show an effective resolution with realistic switched-capacitor load greater than 15 bits, being a suitable solution for the static test of ADCs with effective resolutions in the order of 12 bits and 80 Msps of sampling frequency.

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

A comprehensive system for real-time monitoring of a set of cell-cultures using a Voltage Oscillation (VO) methodology is proposed. The main idea is to connect the bio-electrical elements (electrodes & cell-culture) in such a way that sequentially a suitable electrical oscillator, which only uses a DC power source, is built. Using the employed electrical models given in [1, 2], the attained oscillation parameters (frequency and amplitude) can be directly related to the biological test. A digital circuitry is developed to pick-up the experimental measurements, which are gathered and shown in real-time in a web application.

High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (<; 200fs) are introduced and compared in a 0.18μm commercial CMOS process.