Sajjad Tohidi

Low-voltage ride-through (LVRT) is one of the most important criteria for integrating wind energy into the power grid. Based on grid connection codes, wind generators must remain connected during fault conditions. However, this requires a careful protection scheme design for addressing the successful ride through of the brushless doubly fed induction generator (BDFIG) during severe voltage dips. This paper proposes a comprehensive solution for enhancing the BDFIG ride through during asymmetrical faults. Furthermore, since the proposed solution is dependent on the type and severity of voltage dips, an updated harmonic resilient scheme is developed to detect the dip level and type of faults. Performance of the proposed protection scheme is investigated for further improvement of the brushless DFIG LVRT capability based on series dynamic resistor (SDR) circuit design in order to limit post-fault oscillations. With the proposed solution, the BDFIG can satisfy ride through requirements for severe voltage dip scenarios. The proposed framework which includes a voltage detection method, appropriate SDR value determination procedure, and SDR control circuit was implemented and validated with a coupled circuit model in MATLAB/Simulink for a BDFIG prototype.

Security of smart power systems data points has become a critical issue in recent years. The phasor measurement units transfer the measured data to the central unit for various purposes such as state estimation. Since the connection lines can be vulnerable to cyber-physical attacks, the information security of such sensors should enhance. This paper utilizes firewall hardware to specify a bypass channel and create a secure path for data transferring. Hence, a bi-level modelling is proposed where the optimal place of phasor measurement units is determined in the higher level and the location of firewalls is specified in the lower level. Moreover, impacts of component failure and loss of connection lines are investigated. The simulation results are implemented on the IEEE 8-bus and 14bus standard transmission systems.

This paper presents an improved finite‐control‐set model predictive control (MPC) strategy for the doubly fed induction generator (DFIG). The MPC‐based controller's main drawback is high computational burden, which requires a long time to perform online optimization. In this regard, real‐time implementation becomes impossible in some cases. Thereupon, this paper suggests a variable sampling time in the prediction process to achieve a balance between the prediction horizon and computational burden. In other words, compared to the conventional MPC‐based techniques, longer horizon is predicted with fewer samples. In this method, there are two sampling times including a fixed sampling time for the system discretization structure, and a variable sampling time used in the prediction process. The proposed technique also utilizes a comparative incremental algorithm to prevent checking all possible control inputs over the objective function in order to reduce the computational time further. In addition, a penalty term, which includes the number of switch changes, is added to the cost function to reduce the switching frequency. Both the simulation and experimental results show that the proposed MPC can significantly improve the DFIG control system's performance by increasing the accuracy of tracking response and reducing the computational time. The experimental test is carried out by the hardware in loop system by using TMS320F28338 and PC‐Lab card. The computational delay caused by the digital signal processor and other influential factors are compensated by using the prediction plus prediction approach. The results confirm that the proposed controller has a lower overshoot and power ripple compared to the vector controller and direct torque controller. It also reduces the computational time up to 40% and reduces the average switching frequency by 12% in comparison to the conventional MPC.