Andrey A. Antonov
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Andrey A. Antonov has a total of 18 co-authors. Here are the top co-authors by number of shared publications:
- Maxim S. Gorbunov
IMEC, Leuven, Belgium
5 shared publications Gennady I. Zebrev
Department of Micro- and Nanoelectronics, National Research Nuclear University), Moscow, Russia
4 shared publications- Vladimir V. Emeliyanov
Research Institute of Scientific Instruments, Lytkarino, Moscow, Russia
4 shared publications - Alexander I. Chumakov
National Research Nuclear University MEPhI (Moscow Engineering Physics Institute)
3 shared publications - Alexander I. Ozerov
Research Institute of Scientific Instruments, Lytkarino, Moscow region, Russia
3 shared publications Andrey V. Yanenko
Specialized Electronic Systems (SPELS), Moscow, Russia
3 shared publications
Latest Publications
- 24 June 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 61 (4) , 1575-1582
Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study
We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques.
- 24 June 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 61 (4) , 1575-1582
Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study
We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques.
- 9 June 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 61 (4) , 1597-1602
SET Tolerance of 65 nm CMOS Majority Voters: A Comparative Study
We study the design of different majority voters based on a commercial 65 nm CMOS technology, propose the test system and discuss the experimental results of heavy ion irradiation campaign and the proposed relative efficiency criterion for choosing the voter for a given TMR strategy.
- 9 June 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 61 (4) , 1597-1602
SET Tolerance of 65 nm CMOS Majority Voters: A Comparative Study
We study the design of different majority voters based on a commercial 65 nm CMOS technology, propose the test system and discuss the experimental results of heavy ion irradiation campaign and the proposed relative efficiency criterion for choosing the voter for a given TMR strategy.
- 7 February 2013
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 60 (4) , 2762-2767
Fault-Tolerant SOI Microprocessor for Space Applications
The design and experimental results are presented for the fault-tolerant 0.35 ìm SOI CMOS microprocessor. DICE-like cells are shown to be vulnerable to SEU during “read” and “write” modes.
- 7 February 2013
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 60 (4) , 2762-2767
Fault-Tolerant SOI Microprocessor for Space Applications
The design and experimental results are presented for the fault-tolerant 0.35 ìm SOI CMOS microprocessor. DICE-like cells are shown to be vulnerable to SEU during “read” and “write” modes.
- 7 February 2012
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 59 (4) , 1130-1135
Analysis of SOI CMOS Microprocessor's SEE Sensitivity: Correlation of the Results Obtained by Different Test Methods
The results on SEE sensitivity of 0.5 $\mu$m SOI CMOS microprocessor are presented and discussed. The comparative analysis of different test techniques (particle accelerator, pulsed laser technique and $^{252}$Cf fission source) is provided for the cache. The possible sources of discrepancies between test results and the ways of data correction and methods of testing techniques' accuracy improvement are discussed.
- 7 February 2012
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 59 (4) , 1130-1135
Analysis of SOI CMOS Microprocessor's SEE Sensitivity: Correlation of the Results Obtained by Different Test Methods
The results on SEE sensitivity of 0.5 $\mu$m SOI CMOS microprocessor are presented and discussed. The comparative analysis of different test techniques (particle accelerator, pulsed laser technique and $^{252}$Cf fission source) is provided for the cache. The possible sources of discrepancies between test results and the ways of data correction and methods of testing techniques' accuracy improvement are discussed.
- 1 September 2011
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 03796566,p. 665-668
Analysis of SOI CMOS microprocessor's SEE sensitivity: Correlation of the results obtained by different test methods
The results on SEE sensitivity of 0.5 μm SOI CMOS microprocessor are presented and discussed. The comparative analysis of different test techniques (particle accelerator, pulsed laser technique and 252 Cf fission source) is provided for the cache. The possible sources of discrepancies between test results and the ways of data correction and methods of testing techniques' accuracy improvement are discussed.
- 1 September 2011
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 03796566,p. 665-668
Analysis of SOI CMOS microprocessor's SEE sensitivity: Correlation of the results obtained by different test methods
The results on SEE sensitivity of 0.5 μm SOI CMOS microprocessor are presented and discussed. The comparative analysis of different test techniques (particle accelerator, pulsed laser technique and 252 Cf fission source) is provided for the cache. The possible sources of discrepancies between test results and the ways of data correction and methods of testing techniques' accuracy improvement are discussed.