Dominik Sondej

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

This paper presents a comprehensive analysis of measurement uncertainty of a wide class of precise time interval counters based on the most common two-stage time interpolation method. All nonnegligible sources of errors are discussed, including the quantization process, nonlinearity of time interpolators, timing jitter induced by elements of signal paths as well as inherent jitter of input pulses, and reference clock signal. A formula of the total measurement uncertainty and several design suggestions aiming at improving the time counter accuracy and precision is provided.

We present the design, implementation, and test results of an integrated time digitizer based on a new conversion method that applies multiedge coding in independent coding lines. The proposed method eliminates an existing technological limitation of resolution inherent in the methods based on standard time coding delay lines, which causes that the value of resolution cannot be lower than the propagation time of the fastest delay element in the line. The developed method allows increasing the resolution proportionally to the number of signal edges coded and lines involved. An interpolating time counter designed by applying the six-edge coding in three independent coding lines provides subpicosecond resolution (902 fs), high precision (<;6 ps), and wide measurement range (2 s). A short conversion time of the method and the use of local RAM memory for storing measurement results allowed for significant shortening of the digitizer dead time and achieving the measurement rate up to 6 million measurements per second. The digitizer is implemented in an easily available and cheap field programmable gate array device manufactured in the 45-nm CMOS technology.

This paper presents the comparison of main properties of two recently developed methods for precise time-to-digital conversion based on time coding respectively in independent coding lines and with the use of multi-edge pattern signal. An essential advantage of these methods consists in capability to overcome the technological limitation of conversion resolution of methods commonly used so far. Both methods were used to design two time counters implemented in the same programmable device. Then the counters were tested in identical measurement conditions and obtained results were compared in the context of main metrological, design, technical and economic parameters.

The paper describes a new method for time-to-digital conversion that allows achieving the conversion resolution far below the propagation time of the fastest delay buffer in integrated circuit (IC). The method is a combination of the multi-edge time coding and time digitization in independent coding lines. The implementation of such combination and assessment of its effectiveness are the main aims of this research. The article also describes the main design issues that were solved during the implementation of method in an FPGA device. They include: the generation of a pattern square signal with a certain amount of edges and possibly minimal delays between them, the elimination of bubble errors and reduction of internal interferences in IC.

We present the design, implementation and test results of an integrated time-to-digital converter based on a new method with multi-edge coding in independent coding lines. The method allows to achieve high resolution below 1 ps and short conversion time of about 3 ns. When used in an interpolation time counter it provides standard measurement uncertainty below 6 ps. The converter has been implemented in a readily available and cheap programmable device Spartan-6 (Xilinx). Applying a multiple coding for time digitization in independent coding lines let us decrease the number of parallel coding lines needed to obtain the same high resolution by averaging. This leads to significant reduction of required logical resources of programmable device. Additionally, the high rate of conversion (above 1 million conversions per sec.) has been achieved.

This paper presents the design, operation and test results of an interpolating time counter with a multi-edge coding principle implemented in the second stage of interpolation. The counter is implemented in an FPGA device (Spartan-6, Xilinx) and provides a 2.7 ps resolution, 8 ps precision and 1 s measurement range. The development of such a high performance instrument needs to solve several design problems. The main of them are an implementation of a pattern generator and elimination of bubble errors. We designed and tested two pattern generators based respectively on look-up tables and fast carry chains. The former one is simpler for implementation while the latter allows to control parameters of the pattern signal. This control feature is especially important for the quality of T/D conversion that depends, among others, on the complexity of the pattern signal. We tested three variants of TDC based in turn on coding of three rising, three falling or six alternated edges.