Simone Gerardin

The aggressive scaling of CMOS devices has led to a decreased sensitivity of the gate oxide to Total Ionizing Dose (TID) effects. Currently, the TID tolerance of scaled transistors is primarily related to charge trapping in other thick isolation oxides, such as Shallow Trench Isolations (STI). Moreover, to mitigate the short-channel effects, including the threshold voltage roll-off, drain-induced barrier lowering (DIBL), and punchthrough, modern technologies include non-uniform bulk doping profiles determined by halos and anti-punchthrough (APT) implants. These implants add complexity to the understanding of TID effects related to the charge trapping in the STI. In this work, we combined experimental results with TCAD simulations to highlight the key role of the APT implant in influencing the TID-sensitivity of planar MOSFETs. The results demonstrate that variation in the APT doping, depth, and width significantly impacts the off-leakage current, which is a major concern in irradiated n-MOSFETs. The highest TID tolerance is achieved in transistors designed with the APT implantation depth close to the drain/source extension depth, while the TID degradation of threshold voltage and transconductance is slightly affected by the APT. Notably, these changes in APT implantation parameters may not be evident in the pre-radiation characteristics but can substantially affect the TID resilience. As a result, transistors with different APT implantation profiles exhibit similar pre-rad I_D-V_GS but diverge in their TID sensitivities.

The impact of proton energy on total ionizing dose and displacement damage effects has been investigated in commercial 4H-SiC vertical power MOSFETs at ultra-high doses. Devices were irradiated with 1 MeV and 3 MeV protons, which resulted in different penetration ranges of the primary particles. The corresponding peak in non-ionizing energy loss is located in the epitaxial region for 1-MeV protons and in the substrate of the device for 3-MeV protons. In parallel, deep-level transient spectroscopy was performed on irradiated 4H-SiC wafers to analyze the formation of electrically active defects produced by protons of the same energies. A correlation between electron trap concentration and effective doping reduction was observed, confirming the role of these defects in carrier compensation and their direct impact on the electrical degradation observed in the commercial SiC power MOSFETs.

The capability to operate at high temperature of SiC power MOSFETs makes it essential to assess radiation-induced damage under realistic operating conditions to ensure reliable evaluations of device robustness. This study investigates the total ionizing dose (TID) effects induced by X-rays at different temperatures in vertical SiC power MOSFETs. Irradiation at high temperatures results in smaller threshold voltage (V_TH) degradation than at room temperature, due to enhanced recombination of positively trapped charge during exposure. Nonetheless, when high-temperature annealing is performed after the exposure, the final threshold voltage shift (ΔV_TH) is independent of the irradiation temperature, and solely dependent on the temperature selected for the annealing process. The negligible degradation observed in subthreshold swing, transconductance, and C-V stretch-out indicates minimal activation of interface traps at the SiC/SiO₂ interface, confirming improved interface quality in the latest generation devices.

Flash memories are essential components in modern electronic systems, including space applications that demand high-density, non-volatile storage. This paper provides a comprehensive review of the impact of ionizing radiation, both Total Ionizing Dose (TID) and Single Event Effects (SEE), on Flash memories. While radiation-induced degradation has long been associated with peripheral circuitry, the most scaled planar device generations reveal that memory cells themselves can be increasingly affected as well. The miniaturization of cells and then the shift from planar to 3D architectures introduce new reliability challenges that must be addressed. After outlining the evolution of Flash technology and its main reliability issues, we examine radiation effects on both memory cells and peripheral circuitry, including charge pumps, decoders, page buffers, and embedded controllers. Particular attention is given to cell-level effects: starting from planar Flash fundamentals and extending to 3D devices, with a focus on the two dominant technologies, Floating Gate and Charge Trap (Replacement-Gate) cells.

In real-life operation, electronic devices are exposed at the same time to different sources of ionizing radiation. In this paper, we evaluate the impact of x-rays effects on the alpha-induced soft error rate in 3D NAND Flash memories with replacement gate architecture, one of the most widely used non-volatile technology. Threshold voltage shifts and bit error rates due to alpha particle exposure in devices previously exposed or not to x-rays are studied, focusing on the response of memory cells. Experimental results show that the alpha soft error rate is not significantly affected by previous x-ray irradiation, at least for small doses, well above those commonly used for printed circuit board inspections.

We perform Single Event Effects (SEE) tests with well-characterized fully fragmented (i.e., beyond Bragg peak) high-energy heavy-ion beams and compare the results with those expected from conventional, mono-Linear Energy Transfer (LET) measurements, showing a satisfactory level of agreement between the two. This compliance paves the way to the exploitation of simulation tools for accurately quantifying the ion fragmentation impact on SEE rates for both ground-level testing conditions and space Galactic Cosmic Ray environments with electronics operating behind significant thicknesses of shielding. The satisfactory agreement level is also encouraging in view of the possible usage of fragmented heavy ion beams for ground-level SEE testing of electronics.

Using comprehensive experimental data and 3D Technology Computer-Aided Design simulations, this paper discusses the effects and mechanisms of Total Ionizing Dose (TID) in the lateral Shallow Trench Isolation (STI) in planar CMOS technologies in the 65-28 nm nodes. During irradiation to ultra-high doses, nMOS transistors often exhibit a continuous increase in the off-state (leakage) current, while the evolution of the on-current, threshold voltage, and transconductance show a rebound that is considerably more evident in narrow channel transistors. This difference in the on- and off-state parameters evolution with TID is traceable to variable de-passivation of interface traps in depth along the STI sidewall. While at all depths TID determines a build-up of trapped holes in the STI oxide, only in the shallower portion a significant number of interface traps are gradually de-passivated leading to an accumulation of negative trapped charge. The different dynamics of hole and electron trapping determines the rebound of the on-state parameters in typical high-dose-rate experiments, while the increase in off-current is driven by the constant accumulation of trapped holes at larger depths. In pMOS transistors, where interface traps also get positively charged, the degradation of all parameters is constant with TID, larger than for nMOS, and channel width dependent. This response is consistent across different technology nodes, which highlights the fundamental role of the STI oxide in determining the TID tolerance of MOS transistors in planar technologies with very thin gate oxide (< 5 nm).

This study explores the total ionizing dose (TID) and displacement damage (DD) effects in trench silicon carbide (SiC) power MOSFETs. The effects of X-ray irradiation reveal significant negative shifts in the threshold voltage, particularly evident in devices biased with positive gate bias. The TID effects in those devices are visible at doses as low as 10 krad(SiO ₂ ), indicating the higher TID sensitivity of trench devices compared to some planar counterparts. Exposure to 3-MeV protons leads to substantial reductions in drain current induced by a fall in the transconductance, while no damage to the gate oxide is observed up to doses of 50 Mrad(SiO ₂ ). The substantial degradation of transconductance indicates DD, which become prominent at doses exceeding 10 Mrad(SiO ₂ ). Both trench and planar devices exhibit similar DD-induced effects, suggesting a common underlying mechanism linked to defects within the epitaxial SiC layer.

The incessant scaling in the integration density of 3D NAND Flash memories is mostly achieved through the combination of wordline stacking and reduction of the distance between wordlines (tier pitch). In this paper, the impact of tier pitch scaling on total ionizing dose sensitivity of 3D NAND Flash cells is investigated in memories using charge-trap technology, in terms of threshold voltage shifts and raw bit errors. Experimental results show a mild dependence of TID effects on the tier pitch. The physical mechanisms are discussed, and possible scaling trends are analyzed.