Guang-Ming Tang

The magnetic fields induced by the bias currents and the return currents flowing on a ground plane have a great influence on the performance of complex rapid single flux quantum (RSFQ) circuits. Conventional approach applies equal negative bias currents to the ground contacts adjacent to the bias supply contacts to alleviate this problem, but this strategy may not be optimal when the power supply network is complex. We propose a new test approach to adjusting the negative bias currents independently. By changing the current distribution and thereby altering the spatial distribution of the magnetic field across the chip, this approach can make the circuit work, or make the circuit work more stably. Experimental validation on two 8-bit RSFQ CPUs demonstrated the approach's efficacy: redistributing negative currents restored functionality in a nonoperational circuit and eliminated the intermittent failure in another. These results highlight the critical role of adjusting current distribution in overcoming magnetic interference, offering a practical solution for testing and optimizing the power supply of complex RSFQ circuits where conventional approach falls short.

Current artificial intelligence faces challenges in improving computational efficiency due to increasing scale and complexity. Superconducting circuit, as one of the most promising technologies in the post-Moore era, offers ultrahigh-speed computation and ultralow power consumption. Superconducting circuits are driven by pulses, which enables direct execution of pulse-based neuromorphic computing. Consequently, superconducting circuits hold the potential to facilitate higher efficiency and larger scale neuromorphic chips. However, existing efforts neglect the limitations and constraints of superconducting circuits, such as the extra overhead of pulse-based logic, the lack of superconducting memory, and low integration. Hence, their work cannot be utilized in fabricating real superconducting neuromorphic chips. This article introduces superconducting spiking neural network (SSNN), which aims to enable full neuromorphic computing on superconducting circuits. The design of SSNN addresses key issues including a superconducting circuit-based neuron model, weight processing methods suitable for superconducting pulses, and superconducting neuromorphic on-chip networks. SSNN enables complete neuromorphic computing on superconducting circuits. We validate the feasibility and accuracy of SSNN using a standard cell library of superconducting circuits and successfully fabricate the world's first superconducting neuromorphic chip. Our evaluation demonstrates a remarkable $50\times$ increase in power efficiency compared to state-of-the-art semiconductor designs.

Due to power consumption and speed limitations, the development of CMOS-based large-scale integrated circuits has stagnated in the post-Moore era. While superconducting digital integrated circuit is a promising solution due to its low power consumption and latency. However, the lack of large-scale cryogenic storage units prevents most superconducting chips from being deployed in practical applications. To fully utilize the advantages of superconducting chips and successfully apply them in processing large datasets, we propose a novel heterogeneous processor based on CMOS-based circuits and superconducting chips for processing pattern-matching tasks. In our proposed architecture, a novel communication architecture that enables high-speed, reliable communication between 12GHz superconducting chips and CMOS circuits is proposed. The hardware overhead for high-speed communication in superconducting chips can be minimized by this approach. Additionally, the data communication rate of a single channel can reach 12Gbps. Simultaneously, we present a 12GHz, large-scale superconducting chip with 6286 Josephson Junctions that can perform 16-bit pattern matching using the SIMIT-Nb03 process. We have successfully applied our proposed heterogeneous processor to the gene sequence alignment. The processor that uses only one superconducting chip has a throughput of 1.5 Gbp/s (billion base pairs per second), whereas a processor with two superconducting chips has 3 Gbp/s.

The rapid single-flux-quantum (RSFQ) superconducting technology is highly promising due to its ultra-high-speed computation with ultra-low-power consumption, making it an ideal solution for the post-Moore era. In superconducting technology, information is encoded and processed based on pulses that resemble the neuronal pulses present in biological neural systems. This has led to a growing research focus on implementing neuromorphic processing using superconducting technology. However, current research on superconducting neuromorphic processing does not fully leverage the advantages of superconducting circuits due to incomplete neuromorphic design and approach. Although they have demonstrated the benefits of using superconducting technology for neuromorphic hardware, their designs are mostly incomplete, with only a few components validated, or based solely on simulation. This paper presents SUSHI (Superconducting neUromorphic proceSsing cHIp) to fully leverage the potential of superconducting neuromorphic processing. Based on three guiding principles and our architectural and methodological designs, we address existing challenges and enables the design of verifiable and fabricable superconducting neuromorphic chips. We fabricate and verify a chip of SUSHI using superconducting circuit technology. Successfully obtaining the correct inference results of a complete neural network on the chip, this is the first instance of neural networks being completely executed on a superconducting chip to the best of our knowledge. Our evaluation shows that using approximately 105 Josephson junctions, SUSHI achieves a peak neuromorphic processing performance of 1,355 giga-synaptic operations per second (GSOPS) and a power efficiency of 32,366 GSOPS per Watt (GSOPS/W). This power efficiency outperforms the state-of-the-art neuromorphic chips TrueNorth and Tianjic by 81 and 50 times, respectively.

In comparison to the widely-used CMOS circuits, superconducting Rapid Single Flux Quantum (RSFQ) circuits offer advantages such as fast operating frequency and low power consumption, making them a potential direction for development in the post-Moore era of digital circuits. However, designing RSFQ CPUs faces challenges, one of which is the need for a compact register file. This is because, under current RSFQ circuit process conditions, the memory module typically occupies a large chip area. This paper proposes a newly-designed Write-controllable Non-Destructive Read Out cell (WNDRO) that can limit the data writing pulse input to change the internal state of the cell. Based on the WNDRO, a compact RSFQ register file is designed that can realize random, non-destructive data reading. Additionally, a global write strategy is applied to omit the data write routing circuit and the reset control module, and the circuit design of the read and write control module is optimized. In comparison to general designs, the proposed compact register file design will save a large number of Josephson Junctions and effectively reduce the chip area. Additionally, this paper proposes several optimization logic designs for RSFQ CPU designers as a reference.

Deep-learning techniques have significantly improved object detection performance, especially with binocular images in 3D scenarios. To supervise the depth information in stereo 3D object detection, reconstructing the 3D dense depth of LiDAR point clouds causes higher computational costs and lower inference speed. After exploring the intrinsic relationship between the implicit depth information and semantic texture features of the binocular images, we propose an efficient and accurate 3D object detection algorithm, FCNet, in stereo images. First, we construct a multi-scale cost–volume containing implicit depth information using the normalized dot-product by generating multi-scale feature maps from the input stereo images. Secondly, the variant attention model enhances its global and local description, and the sparse region monitors the depth loss deep regression. Thirdly, for balancing the channel information preservation of the re-fused left–right feature maps and computational burden, a reweighting strategy is employed to enhance the feature correlation in merging the last-layer features of binocular images. Extensive experiment results on the challenging KITTI benchmark demonstrate that the proposed algorithm achieves better performance, including a lower computational cost and higher inference speed in 3D object detection.

A 128-b rapid single-flux-quantum (RSFQ) Advanced Encryption Standard (AES) encryption accelerator based on bit-slice architecture is proposed for the first time. Unlike the traditional methods, the method of looking up only one 256-B table to complete the entire AES round function is proposed. The proposed method can reduce nearly 50% of the hardware cost compared to the traditional method. The simple lookup table, shift, and xor operations are used in the proposed accelerator where one 256-B table needs to be stored for lookup table operations. The RSFQ logic circuits of the proposed accelerator are designed and simulated at the logic level. It consists of 136 558 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2. The simulation results show the proposed accelerator works correctly.