Yuling Niu

This paper presents an accurate experimental method to determine the effective strain for the advanced electronic packages with heterogeneous structure or multiple composite layers when the out-of-plane deformation has evident effects on the in-plane strain quantification. The experimental results rely on the 3-D digital image correlation (DIC) technique, a full-field optical measurement method. Several advantages make this technique a perfect choice for characterizing the effective strain for electronic packages, especially for the heterogeneously designed packages that are likely to have large warpage after reflow process. In order to generate the effective strain with the consideration of warpage and thickness effects, an improved data process algorithm for 3-D DIC is introduced to obtain the neutral plane strain. The result was validated analytically and numerically based on the Timoshenko beam theory and finite-element method. The effectiveness and necessity of this paper are demonstrated by applying the results into a practical multilayer package and forecasting the accurate behavior under thermal loading.

In this study, the moisture induced delamination behavior of a plastic ball grid array package under the solder reflow process was investigated by the finite element analysis. The entire moisture history of the PBGA package was simulated for preconditioning at moisture sensitivity level 1 and the subsequent exposure to a soldering reflow. A fracture mechanics based analysis was used to investigate the combined effects of temperature, moisture and vapor pressure on the delamination behavior at the die/molding compound and die/die attach interfaces during solder reflow. For determining the total strain energy release rate and total stress intensity factor under a multiphysics environment like reflow, researchers commonly used the principle of superposition to combine the results from individual thermal stress, hygroscopic stress and vapor pressure induced stress analyses. In this study, a new method was proposed to obtain the total strain energy release rate and total stress intensity factor under the multi-physics environment in a single fracture analysis instead of three. Two different methods-virtual crack closure technique (VCCT) and crack tip opening displacement method (CTOD) were employed and compared in studying the variation of strain energy release rates during lead-free solder reflow. The relationship between the strain energy release rate and crack length was also obtained. The developments of the stress intensity factors due to individual effect of thermal mismatch, hygroscopic swelling and vapor pressure were calculated. The mode mixity was also determined under different temperatures and crack length.

Three-dimensional (3-D) digital image correlation (DIC) has been gradually adopted by industry these years. This method utilizes a pair of cameras to accumulate and correlate images through tracking the movement of features on the specimen surface in real time. It is capable of generating both in-plane and out-of-plane deformation during one test. To some extent, it is perfect to be utilized in the reliability analysis for electronic packages due to its high measurement accuracy and adjustable field of view. Therefore, it attracts much attention from the electronic packaging area. In this work, several reliability studies of the electronic packages with 3-D DIC system were introduced. The advantages of DIC were discussed and some features were compared to the conventional measurement methods. At the same time, the methodology, to make full use of this technique to achieve most information with DIC system, was described. With one DIC system, the 2-D strain measurement of solders, micro-bumps and the underfill can be done to learn the internal residual stress and strain distribution under loading. Meanwhile, both CTE and warpage results were generated by the 3-D DIC experiment by one measurement for assessing the reliability of the packages and validating the effectiveness of the finite element models.

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls and bottom. A polymer is used to fill the rest of the cavity. Stresses in risk sites are studied and ranked for this TSV structure by FEA modeling. Parametric studies for material properties (modulus and thermal expansion) of TSV polymer are performed. The second type is a high aspect ratio TSV filled by polycrystalline silicon (poly Si). Potential risks of the voids in the poly Si due to filling defects are studied. Fracture mechanics methods are utilized to evaluate the risk for two different assembly conditions: package assembled to printed circuit board (PCB) and package assembled to flexible substrate. The effect of board/substrate/die thickness and the size and location of the void are discussed.

Conventional reflow method in a convection oven is the principal step during the package assembly process in order to guarantee high productivity and make full use of the self-alignment. The package behavior, especially warpage, has significant effects on assuring package assembly reliability during the reflow process. In recent decades, several techniques, like Shadow Moiré or 3-D digital image correlation (DIC), have been developed to assist industry in characterizing warpage. The requirement of artificial speckles on the specimen surface inevitably reduces the measurement accuracy and contaminates the specimen. To improve the accuracy and keep the specimen clean, a novel in situ warpage measurement method without surface treatment is developed, and its result is demonstrated. The specimen can be reapplied to the manufacturing process after the measurement, and one sample can be assessed consistently at different assembly process steps instead of wasting samples at each assembly stage.

The decreasing size of solder joints leaves limited tolerance of allowable warpage range for successful assembly. Understanding the electronic packages' behavior during the reflow process becomes one of the most important tasks in developing assembly process and assuring reliability. Three-dimensional (3D) digital image correlation (DIC) plays an important role in quantifying warpage of BGA packages under thermal loading. To measure warpage of the substrate surface of a BGA package, conventional 3D DIC technique requires removing the solder balls, which takes the risk of damaging the solder mask surface and influences on measurement accuracy. Three parameters of 3D DIC (camera angle, facet size and facet step) are studied on the effects of data integrity and accuracy to realize warpage measurement while solder balls are attached to the packages. This method introduces novel settings of these parameters compared to current 3D DIC requirements, and summarizes a guidance for implementing nondestructive warpage measurement with different sizes of solder balls and camera resolutions.