Sensen Li

This article introduces Doherty active load modulation into low-noise amplifier (LNA) designs to dynamically enhance linearity. Under nominal small-signal conditions, the proposed LNA operates like conventional counterparts, consuming no additional power. When strong in-band blockers are present, auxiliary paths are adaptively engaged to activate a high-linearity mode without incurring a noise penalty. The proposed design effectively overcomes the conventional tradeoff between linearity and other key LNA performance metrics. Building on the main concept, two additional techniques were employed to further enhance linearity: dedicated gain expansion and multi-way Doherty architecture. These techniques led to the development of the two implemented prototypes presented in this article. Both designs achieve over 10-dB improvement in input 1-dB compression point (IP ${}_{1\mathrm {dB}}$ ) while maintaining a minimum noise figure (NF) of 2.5dB. Modulation testing was conducted in the presence of in-band blockers, demonstrating successful demodulation of a 400-MHz 64-QAM desired signal with less than 5% EVM, even under 20 dBc in-band 100-MHz 16-QAM blockers.

This work presents a high-efficiency D-band power amplifier (PA) implemented in 250-nm indium phosphide (InP) technology. A key innovation is the integration of artificial intelligence (AI) into the radio frequency power amplifier (RFPA) design flow for the automated generation of passive networks—a traditionally labor- and computation-intensive process. By utilizing a machine learning (ML) model as a surrogate for time-consuming electromagnetic (EM) solvers, this approach enables rapid exploration of a broader design space, improving productivity and uncovering potentially nonintuitive structures. The physics augmentation in the ML model mitigates its dependence on big training datasets, achieving an S-parameter prediction error of less than 0.5 dB at the target frequency of 125 GHz. Using fully AI-generated passive networks, the PA delivers a saturated output power ( ${P} _{\text {sat}}$ ) of 15.3 dBm and a peak power-added efficiency (PAE) of 26%. Additionally, it achieves a peak gain of 12.7 dB and a 3-dB bandwidth spanning 110–140 GHz and demonstrates its capability to support high-order quadrature amplitude modulation (QAM) signals at tens of Gb/s data rates.

While AI for EDA has seen great success in digital IC design and some success in analog design, its potential for enabling RFIC design is yet to be fully explored. Due to its high-frequency nature, RFIC involves challenges such as parasitic effects, electromagnetic interference (EMI), signal integrity (SI), and other non-idealities. The modeling of passive networks and the associated computationally expensive EM simulations remain the major bottleneck in manual RFIC designs. This paper discusses the challenges and opportunities in ML-assisted RFIC design, covering topics from physics-augmented surrogate modeling to the inverse design of passive structures.

This article presents a $V$ -band (i.e., 47-75 GHz) differential four-way distributed-active-transformer (DAT) power amplifier (PA), which uses hybrid NMOS/PMOS for double nonlinearity cancellation to improve the linearity with minimal impact on the overall PA efficiency. Implemented in the 45-nm CMOS silicon-on-insulator (SOI) process, the proposed PA consists of three stages, pre-driver, driver, and PA stages, to deliver the desired gain at the $V$ -band. The PA stage includes both NMOS and PMOS transistors, while the driver stage adopts PMOS and the pre-driver stage uses NMOS transistors. This mixed NMOS/PMOS scheme provides a high-order nonlinearity cancellation, substantially improving the PA linearity, and optimizes its performance. An ultra-compact differential four-way series–parallel DAT-based power combiner is used to provide the optimum load (R $_{\text{opt}}$ ) to the mixed NMOS/PMOS PA. This proposed PA output matching network/power combiner only occupies one transformer footprint, resulting in a reduced chip area and design complexity. The PA achieves peak power-added-efficiency (PAE) of 35.4%, saturation power (P $_{\text{sat}}$ ) of 16.3 dBm, and AM–PM distortion $<$ 2 $^{\circ}$ (at output 1-dB compression point–13.5 dBm) in 50.4-58 GHz. The AM–PM distortion drops $<$ 0.5 $^{\circ}$ at 55 GHz. The PA exhibits an average PAE (PAE $_{\text{avg}}$ ) of 15.6% and rms error vector magnitude (EVM) $<$ $-$ 25 dB when transmitting a 64-QAM modulated signal with 9.5 dBm average output power (P $_{\text{avg}}$ ) at 0.5 GSym/s. The EVM remains better than $-$ 24 dB at 3 GSym/s with P $_{\text{avg}}$ of 8.1 dBm (PAE $_{\text{avg}}$ $=$ 9.1%). In addition, this PA is measured by 5G NR CP-OFDM 64-QAM modulation with multiple CCs. When using 1-CC FR2 400-MHz modulation, it achieves PAE $_{\text{avg}}$ of 14.5%, P $_{\text{avg}}$ of 10 dBm, EVM of $-$ 23.5 dB, and adjacent channel power ratio (ACPR) of $-$ 25.8 dBc. For 4-CC FR2 200-MHz modulation, the PA exhibits PAE $_{\text{avg}}$ of 8.1%, P $_{\text{avg}}$ of 8 dBm, EVM of $-$ 24.6 dB, and adjacent power channel ration (ACPR) of $-$ 24.6 dBc.

This article presents a millimeter-wave (mmWave) power-combined Doherty power amplifier (PA) topology. To reach watt-level output power and simultaneously enhance back-off efficiency, we propose a multifunctional PA network based on an extended rat-race coupler, which enables the following: 1) parallel Doherty load modulation; 2) multiway series power combining; and 3) differential to single-ended conversion. As proof of concept, a 38-GHz PA prototype is implemented in the GlobalFoundries 45-nm CMOS SOI process. It demonstrates 27.5-dBm saturated power ( $P_{\rm SAT}$ ), 26.9-dBm output 1-dB compression point ( $P_{1\,\text{dB}}$ ), and 15.0% power-added efficiency (PAE) at 6-dB back-off. Among recently reported 30–50-GHz silicon-based high-power PAs with $>$ 23-dBm $P_{\rm SAT}$ , our design demonstrates the highest $P_{1\,\text{dB}}$ and PAE at 6-dB back-off. Tested under 200-MSym/s 64-QAM modulation, the PA achieves 20.0-dBm average output power ( $P_{\rm avg}$ ) and 12.2% average efficiency (PAE $_{\rm avg}$ ).

This article presents a millimeter-wave (mmWave) three-way Doherty output network and its silicon implementation at 38 GHz for 5G new radio (NR) orthogonal frequency-division multiplexing (OFDM). The proposed network synthesis methodology can realize impedance levels that are close to the ideal three-way Doherty operation, reduce the impedance transformation ratio at back-off, and directly absorb the device’s parasitic capacitance. Its design procedure and tradeoffs are discussed in detail. A 38-GHz power amplifier (PA) prototype is implemented in the GlobalFoundries 45-nm CMOS SOI process, achieving 13.7%/11.0% power-added efficiency (PAE) at the 9.5-/11.5-dB back-off, which is among the highest compared with recently reported silicon PAs operating at 35 GHz and above. Tested under 1- and 2-component carrier (CC) 5G NR FR2 64-QAM OFDM signals in the Band n260, the PA demonstrates state-of-the-art average output power (11.3 dBm) and average efficiency (14.7%) with −25-dB error vector magnitude (EVM). The design robustness and reliability are further demonstrated through the testing of multiple samples and PA lifetime.

Next-generation millimeter-wave (mm-Wave) power amplifiers (PAs) need to support multistandard communication systems with wide bandwidth, complex modulation, and high energy efficiency. Most existing mm-Wave PA architectures with power backoff (PBO) efficiency enhancement, such as Doherty and outphasing PAs, typically only support limited carrier bandwidth. In this work, we propose and demonstrate that a 180 $^{\circ}$ coupler balun structure can serve as an extremely wideband active load modulation network for broadband PBO efficiency enhancement and further realize a coupler balun load-modulated PA (CBMA). Moreover, compared to load-modulated balanced amplifiers (LMBAs), the proposed CBMA supports natural single-ended-to-differential balun conversion, differential power cells, and wideband capacitive neutralization, ideal for integrated mm-Wave PAs. Furthermore, we propose a continuous-mode CBMA operation with role exchanges to attain a nearly 3:1 carrier bandwidth. A prototype CBMA is designed and fabricated in a 45-nm RF CMOS SOI process, which achieves an OP $_{\mathrm{1\,dB}}$ PAE of 39.9%–20.4% with OP $_{\mathrm{1\,dB}}$ of over 21.6–18.3 dBm from 26 to 60 GHz. The PA also achieves a 32.8%–13.4% 6-dB PBO (from OP $_{\mathrm{1\,dB}})$ efficiency with its best 1.75 $\times$ /3.51 $\times$ efficiency enhancement over an ideal Class-B/-A PA. Using a single-carrier 64-QAM signal with 0.5 GSym/s (3 Gb/s), the PA supports an average $P_{\mathrm{out}}$ of 15.8–11.3 dBm with an average PAE of 27.15%–8.58% with $-$ 23-dB rms error vector magnitude (EVM) over 26–60 GHz. The PA also supports 5G NR modulation using 5G new radio (NR) FR2 200-MHz 1-CC 64-QAM signals, achieving 18.22%–6.55% average PAE at 10.72–7.1-dBm average $P_{\mathrm{out}}$ with rms EVM of $-$ 23 dB over 26–60 GHz.

This article presents a fully integrated multi-modal CMOS cellular sensor/stimulator array chip with 21 952 pixels and 1568-pixel concurrent readouts, while each array pixel can be independently reconfigured to support three sensing and one stimulation modalities: cellular potential recording, optical-point impedance sensing, and bi-phasic current stimulation. The CMOS sensor/stimulator array chip provides 3.6 mm × 1.6 mm active field-of-view (FoV). Each pixel contains one 8 μm × 8 μm gold deposited electrode, one 6 μm × 6 μm photodiode, and in-pixel circuits within 8 μm × 11 μm pixel area, while the pixel-to-pixel pitch is 16 μm × 16 μm. As a proof of concept, the CMOS array is implemented in a standard 130-nm BiCMOS process. Comprehensive electrical testing (potential/optical/four-point impedance/stimulation) and biological measurements (potential/optical/four-point impedance) with on-chip rat cardiomyocytes demonstrate the functionalities and unique advantages of this multi-modality cellular array. With high throughput multi-modal cellular sensing supported at the pixel level, this array chip enables holistic characterization of on-chip cellular samples with single-cell resolution.

This paper presents a millimeter-wave power amplifier that utilizes a doubly hybrid NMOS/PMOS nonlinearity cancellation technique, demonstrating superior PA linearity performance with extremely low AM-AM and AM-PM distortions. It covers the V-band frequencies of 50.4GHz-58GHz with 35.4% maximum PAE, 16.3dBm saturated power, and only 0.4° AM-PM distortion at the carrier frequency of 55GHz. The measured AM-PM distortion is below 2° over 50-57GHz. Also, this PA supports 64-QAM modulation with 15.6% average PAE and 9.5dBm average output power at 0.5GSym/s (3Gb/s), demonstrating the best PA modulation performance at V-band frequencies below −25dBc rms EVM. Additionally, this is the first V-band PA measured at 64-QAM 3GSym/s (18Gb/s) modulation and 5G NR CP-OFDM 64-QAM FR2 modulations with various modulation bandwidths (e.g., 400MHz and 800MHz) and component-carriers (e.g., 1-CC and 4-CC).