Rajeshwari Pandey

In this paper, we propose a three-port circulator circuit based on operational transconductance amplifiers (OTAs) that features a resistorless topology, categorizing it as a type-A circulator. The behavior of the proposed structure is analyzed in the presence of OTA nonidealities, with corresponding mathematical formulations presented. The functionality of the circuit is verified through SPICE simulations using 180[ ]nm CMOS technology parameters. We also examine the circuit’s performance across various process corners, as well as under supply and temperature variations, finding that the port behavior remains consistent. Additionally, the impact of process variation is assessed through Monte Carlo simulations comprising 100 runs, revealing that the circuit exhibits minimal sensitivity, with the mean frequency at port 2 being 1.006[ ]MHz and a standard deviation of 493[ ]Hz. The linearity of the proposed circuit is evaluated, showing a total harmonic distortion (THD) variation of less than 2%.

This paper presents two new transconductance-boosted architectures of the voltage differencing transconductance amplifier (VDTA). The first architecture (VDTA-I) relies on the technique of transconductance enhancement using partial positive feedback which is realized through negative impedance implemented using a cross-coupled amplifier. The second architecture (VDTA-II) incorporates the concept of gate-to-source voltage enhancement using an inverting amplifier for transconductance boosting. Detailed mathematical formulations for computing transconductance gain and bandwidth are presented using high-frequency small-signal equivalent circuits of both propositions. The functionality of the proposals is validated through SPICE simulations using TSMC 0.18 [ ]m technology parameters. Both DC and AC analyses are carried out through simulations. An enhancement in transconductance gain of 140% is observed for VDTA-I whereas for VDTA-II it is found to be 53% in comparison to the conventional VDTA. The 3 dB frequencies are recorded to be 160 and 630 MHz, respectively. The PVT analyses are also carried out to test the efficacy of both propositions.

This paper examines the temperature impact on the characteristic parameters of a negative capacitance based device structure Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET). Here, Zr-doped HfO 2 (HZO) ferroelectric material is employed as gate stack along with Titanium Nitride (TiN) and Silicon dioxide (SiO2). HZO ferroelectric material generates negative capacitance (NC) effect during the device operation. The main focus of this work is to investigate the dc characteristics of the device in terms of threshold voltage ($\mathbf{V}_{\mathbf{TH}}$), subthreshold swing (SS), on current (Ion) and switching ratio ($\mathbf{I}_{\text {on }} / \mathbf{I}_{\text {off }}$) at different temperatures. Further, the reported device shows better performance in comparison to the Junctionless Ferroelectric Field Effect Transistor (JL-FE-FET).

This paper presents a method for capacitance scaling of Fractional Capacitor (FC) which is implemented using Current Feedback Operational Amplifiers (CFOA) based Capacitance Multipliers (C Multipliers). The circuit facilitates the change in FC value without changing component values in R-C network used for FC modelling or fabricating a new FC. The performance of the proposed circuit is examined for non ideal effects of CFOA. Effective impedance of scaled FC is examined through MATLAB simulations. The functionality of the realized scalers is verified using SPICE simulations where the FC is modelled using domino RC ladder network. Simulation results for impedance magnitude and phase responses are presented for various scaling factors and are compared with theoretical counterparts. The circuit application of proposed FC scaler is demonstrated through implementation of fractional order lossy and lossless integrators; and may be extended to fractional order filters, oscillators, controllers etc.