Amandeep Singh

This paper presents low power circuit design using dynamic gate diffusion input (GDI) technology in Carbon nanotube field effect transistor (CNTFET) technology. GDI technique offers low power with fewer transistor counts and less complexity of circuit and CNTFET technology offers low short channel effect (SCE). NAND and XOR gates-based full adder and two-bit multiplier is designed using the GDI technique and performance analysis is done for various parameters namely power consumption, delay, and power delay product (PDP). Results show that NAND gate-based circuits perform better than XOR-based circuits. Also dynamic GDI NAND gate-based circuits accounts for less power with more flexibility as compared to conventional CMOS-based NAND gate circuits.

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

The major drawbacks of basic electronic components i.e., Vacuum Tubes used before the 1960s were a large size and the inability of these to be scaled down further. With the emphasis shifting to scaling down we came across the MOSFETs in single-gate configuration since the 1960s, they are utilized nowadays in the nanometer region for keeping the high-performance level but still, these single-gate configurations of MOSFETs suffer from different parameters such as coupling, interfacing, channel mobility, channel orientation, switching delay, latch-up and leakage current, short channel effects (DIBL, GIDL, subthreshold swing) and volume inversion and this has led to decrease in inversion charge, increase in leakage current and reduction in the drive current leads us to the exploration of the double-gate configuration of MOSFET and on further exploration it leads us to the novel and higher mobility channel materials such as Si1-xGex which can perform and even shows better results than prevailing single-gate MOSFETs. This paper analyses the different configurations of Si1-xGex for double-gate configuration of MOSFETs and its Future Applications.

This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated CNTFET (TG-CNTFET) & gate all around CNTTFET (GAA-CNTFET). Dual chirality technique is used to design TCAM cell i.e. different chirality for n-type CNTFET & p-type CNTFET which utilizes different threshold voltages and hence improve the performance. Comparative analysis has been done for various parameters viz. Static noise margin (SNM), delay, power and power delay product (PDP). It has been found that GAA-CNTFET based TCAM gives better SNM and power as compared to TG-CNTFET based TCAM, however TG-CNTFET based TCAM gives less delay. However overall PDP is less in GAA-CNTFET which make is suitable for circuit applications as compared to TG-CNTFET.

This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated CNTFET (TG-CNTFET) & gate all around CNTTFET (GAA-CNTFET). Dual chirality technique is used to design TCAM cell i.e. different chirality for n-type CNTFET & p-type CNTFET which utilizes different threshold voltages and hence improve the performance. Comparative analysis has been done for various parameters viz. Static noise margin (SNM), delay, power and power delay product (PDP). It has been found that GAA-CNTFET based TCAM gives better SNM and power as compared to TG-CNTFET based TCAM, however TG-CNTFET based TCAM gives less delay.

In this era of nanotechnology, nanowires (NWs) propose potential impact on electronics, computing, memory, data storage, communications, manufacturing, health, medicine, national security, and other economic sectors as well. NWs offer excellent surface-to-volume ratio (interface phenomena), low defect density, high optical output, and controllable n-type conductivity, making them more appropriate and sensitive for sensing applications. NWs with their ultra-sensitive and real-time detection capabilities lend their applications in nanobiosensors, chemical sensors, gas sensors, and electrochemical sensors. NWs have been used in improving the optical absorption as well as for the collection efficacy in photovoltaic devices. NWs having small size, low weight, low cost for mass production, and are also compatible with commercial planar processes for large-scale circuitry. In the chapter, the authors are focusing to summarize the recent advances in NWs with their potential applications in various fields such as research, health, security, education, entertainment, and power generation.

In recent years, carbon nanotube (CNT) emerged as one of the promising materials that shows various advantages over silicon material (e.g., aggressive channel length scaling due to absence of mobility degradation, variable bandgap with single material, ultra-thin body device that is possible due to smaller diameter [1-3nm], and compatibility of CNT with high-k materials resulting in high ION). Moreover, CNTs show both metallic and semiconducting properties; hence, by using metallic CNTs, interconnects can be realized to fabricate a circuit purely consisting of CNTs. This chapter will provide introduction to carbon nanotubes field effect transistor (CNTFETs) starting from material properties of carbon nanotubes and followed by how it can be used as semiconductor channel in field effect transistor (MOSFET) to form CNTFET. The different types of CNTFETs will be discussed based on the type of CNT used along with their advantages and disadvantages.