Hailong Jiao

A linear time‐variant analysis method for the type‐II all‐digital phase‐locked loop (ADPLL) is proposed to provide a precise frequency response analysis in this paper. From this analysis, a universal stability criterion for ADPLL is established, and the relationship between the maximum phase margin and loop bandwidth is revealed. The analysis indicates that one half of the reference frequency is the zero‐PM upper limit of the unit‐gain bandwidth, whereas practical ADPLL designs with a positive PM must operate below this limit. The proposed theory is verified through extensive simulations and can provide an important guide for the design and optimization of various ADPLL schemes.

A 15-transistor (15T) SRAM cell based fully-digital CIM macro is proposed for AI accelerations. The CIM macro not only supports simultaneous read + write + MAC operations, but also supports ultra-wide-range voltage scaling, digital design flow, and cell-wise bit interleaving. A fine-grained weight update scheme is introduced to perform write and MAC operations simultaneously. A specialized twos complement processing strategy is proposed to enable efficient signed MAC operations without sign extension. Fabricated in a 55-nm CMOS technology, the proposed fully-digital CIM macro enhances the peak energy efficiency by up to 3.46W compared with the state-of-the-art digital CIM schemes.

Wearable intelligent devices are essential for the health monitoring of epilepsy patients in non-hospital environment. The existing seizure detection algorithms for wearable health monitoring devices cannot achieve high sensitivity, short detection latency, low false alarm rate (FAR), as well as lightweight computing simultaneously. In this paper, we propose a two-stage prediction + detection framework, PDNet, for real-time epileptic seizure monitoring. The proposed two-stage PDNet framework consists of a lightweight seizure predictor and a highly-accurate seizure detector. Only when the first-stage seizure predictor forecasts an impending seizure, the second-stage seizure detector is activated to precisely and rapidly classify the seizure states, thereby significantly reducing the amount of computations. A semi-supervised learning strategy is employed to enhance the decision boundary of the seizure predictor, which is used for EEG pre-processing instead of prediction only. Soft labels are adopted to enable the seizure detector to precisely distinguish the seizure states. The proposed PDNet is evaluated using the CHB-MIT scalp EEG database. The proposed PDNet achieves 99.0% sensitivity, 0.43/h FAR, and 3.52-second detection latency with 3.02M multiply–accumulate (MAC) operations, which are competitive compared to the state of the art in terms of sensitivity, detection latency, FAR, and computation complexity. Furthermore, the fine-grained information such as the occurrence process of seizures demonstrated by soft labels can help the caregivers or clinicians to come up with targeted healthcare and clinical treatments.

Bit-serial computing-in memory with SRAM cells (SRAM-CIM) enables a full set of integer and floating-point arithmetic operations and various data-intensive computations. Carbon nanotube field-effect transistors (CN-MOSFETs) with high scalability, energy-efficiency, and low process thermal budget are attractive to realize high-dense monolithic three-dimensional (M3D) SRAM-CIM. However, CN-MOSFETs possess unique process variations with asymmetric spatial correlations which can significantly influence the performance and reliability of carbon-based SRAM-CIM. In this paper, new M3D-4N4P SRAM-CIM cells with CN-MOSFETs are proposed with optimized profiles for achieving ultra-high integration density while preserving robustness of data-access and computation. Furthermore, the variation-aware bit-wise data-mapping method is proposed for enhancing the performance of carbon-based SRAM-CIM by leveraging the spatial correlations of CN-MOSFETs. By minimizing the area skew of vertically-stacked layers, the areas of proposed M3D-4N4P SRAM-CIM cells are reduced by up to 50.32% compared to the previous 6N2P SRAM-CIM cells assuming carbon nanotube transistor technology. The proposed M3D-4N4P SRAM-CIM array also achieves by up to 2.17 $\times$ higher throughput on arithmetic operations and 18.34% lower computing latency with 25.36% reduced energy consumptions on MAC-based benchmarks, respectively, compared to the previous 2D-6N2P SRAM-CIM array.

A digital SRAM-based Computing-in-Memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. An 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves 6.9× @ 1.2 V in energy and 2.33× in area compared with the conventional statistics counters in a 55-nm CMOS technology.

Transformer-based deep learning networks are revolutionizing our society. The convolution and attention co-designed (CAC) Transformers have demonstrated superior performance compared to the conventional Transformer-based networks. However, CAC Transformer networks contain various nonlinear functions, such as softmax and complex activation functions, which require high precision hardware design yet typically with significant cost in area and power consumption. To address these challenges, SoftAct , a compact and high-precision algorithm-hardware co-designed architecture, is proposed to implement both softmax and nonlinear activation functions in CAC Transformer accelerators. An improved softmax algorithm with penalties is proposed to maintain precision in hardware. A stage-wise full zero detection method is developed to skip redundant computation in softmax. A compact and reconfigurable architecture with a symmetrically designed linear fitting module is proposed to achieve nonlinear functions. The SoftAct architecture is designed in an industrial 28-nm CMOS technology with the MobileViT-xxs network classifying the ImageNet-1k dataset as the benchmark. Compared with the state of the art, SoftAct improves up to 5.87% network accuracy under 8-bit quantization, 153.2× area efficiency, and 1435× overall efficiency.

Point cloud is increasingly used in a variety of applications. Farthest Point Sampling (FPS) is typically employed for down-sampling to reduce the size of point cloud and enhance the representational capability by preserving contour points in point cloud analysis. However, due to low parallelism and high computational complexity, high energy consumption and long latency are caused, which becomes a bottleneck of hardware acceleration. In this brief, we propose an adjustable multi-stream block-wise FPS algorithm, adjusted by four configurable parameters, according to hardware and accuracy requirements. A unified hardware architecture with one parameter is designed to implement the adjustable multi-stream block-wise FPS algorithm. Furthermore, we present a rapid searching algorithm to select the optimal configuration of the five parameters. Designed in an industrial 28-nm CMOS technology, the proposed hardware architecture achieves a latency of 0.005 (1.401) ms and a frame energy consumption of 0.09 (27.265) μJ/frame for 1 k (24 k) input points at 200 MHz and 0.9 V supply voltage. Compared to the state of the art, the proposed hardware architecture reduces the latency by up to 99.9%, saves the energy consumption by up to 99.5%, and improves the network accuracy by up to 9.34%.