Herman Jalli Ng
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Herman Jalli Ng has a total of 98 co-authors. Here are the top co-authors by number of shared publications:
Dietmar Kissinger
Institute of Electronic Devices and Circuits, Ulm University, Ulm, Germany
34 shared publications- Dietmar Kissinger
Ulm University
26 shared publications Maciej Kucharski
Circuit Design Department, IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany
15 shared publicationsFrank Herzel
Im Technologiepark 25, 15236 Frankfurt (Oder), IHP, Germany
10 shared publications- Maciej Kucharski
IHP - Leibniz-Institut fr Innovative Mikroelektronik,Frankfurt (Oder),Germany
9 shared publications - Wael Abdullah Ahmad
IHP - Leibniz-Institut für innovative Mikroelektronik, Frankfurt (Oder), Germany
9 shared publications
Latest Publications
- Open Access
- 25 January 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 72 (8) , 4717-4733
Differential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends
Recently, the feasibility of differential-mode power detection for built-in self-test (BIST) in millimeter-wave SiGe transceiver front ends has been demonstrated. In this work, a system analysis of typical BIST scenarios is performed. Specifications for the input power levels as well as the accuracy of power detectors are derived from this analysis. A need for at least two different differential detector architectures is identified. Two detectors are derived from the differential power measurement concept, analyzed, and implemented in the 76–81-GHz automotive radar frequency band. They feature a low power consumption of 500 $\mu$ W and, to the authors’ best knowledge, the lowest published circuit areas of approximately 0.005 mm $^2$ while still being input matched to the differential 100 $\Omega$ system impedance. Both these characteristics are essential to keep the overhead of the BIST minimal. With dynamic ranges of 30 dB and up to 46 dB for the two different architectures, the differential power detector concept can achieve sufficient performance for BIST applications. The robustness against process and temperature effects as well as noise is analyzed and reported for both detectors.
- 25 January 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 72 (8) , 4717-4733
Open AccessDifferential-Mode Power Detection for Built-In Self-Test of SiGe Automotive Radar Transceiver Front Ends
Recently, the feasibility of differential-mode power detection for built-in self-test (BIST) in millimeter-wave SiGe transceiver front ends has been demonstrated. In this work, a system analysis of typical BIST scenarios is performed. Specifications for the input power levels as well as the accuracy of power detectors are derived from this analysis. A need for at least two different differential detector architectures is identified. Two detectors are derived from the differential power measurement concept, analyzed, and implemented in the 76–81-GHz automotive radar frequency band. They feature a low power consumption of 500 $\mu$ W and, to the authors’ best knowledge, the lowest published circuit areas of approximately 0.005 mm $^2$ while still being input matched to the differential 100 $\Omega$ system impedance. Both these characteristics are essential to keep the overhead of the BIST minimal. With dynamic ranges of 30 dB and up to 46 dB for the two different architectures, the differential power detector concept can achieve sufficient performance for BIST applications. The robustness against process and temperature effects as well as noise is analyzed and reported for both detectors.
- 8 May 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (11) , 4855-4868
A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS
Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power V -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz $\textit{f}\textsubscript{T}$ and 500 GHz $\textit{f}\textsubscript{max}$ is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 $\mu$ m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.
- 8 May 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (11) , 4855-4868
A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS
Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power V -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz $\textit{f}\textsubscript{T}$ and 500 GHz $\textit{f}\textsubscript{max}$ is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 $\mu$ m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.
- 17 February 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (8) , 3572-3584
Spur Canceling Technique by Folded xor Gate Phase Detector and Its Application to a Millimeter-Wave SiGe BiCMOS PLL
A folded xor gate (FXOR) phase detector (PD) is proposed for millimeter-wave (mmW) SiGe integer- $N$ phase-locked loops (PLLs) to relax the tradeoff between PLL loop bandwidth and reference spur rejection. With four current-reuse xor gates jointly participated in phase detection, the reference spur generated by each xor gate neutralizes that generated from its complementary counterpart, without degrading the phase margin or incurring extra power. The high gain of the FXOR PD suppresses its noise contribution, and the PD inherently enables frequency tracking together with lock detection. Fabricated in a 130-nm SiGe BiCMOS process, the 80-GHz mmW PLL demonstrates a $-$ 73-dBc reference spur, a minimum integrated jitter of 79.5 fs $_{\mathrm{rms}}$ (10 kHz–100 MHz), and a figure of merit (FoM) of –241 dB.
- 17 February 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (8) , 3572-3584
Spur Canceling Technique by Folded xor Gate Phase Detector and Its Application to a Millimeter-Wave SiGe BiCMOS PLL
A folded xor gate (FXOR) phase detector (PD) is proposed for millimeter-wave (mmW) SiGe integer- $N$ phase-locked loops (PLLs) to relax the tradeoff between PLL loop bandwidth and reference spur rejection. With four current-reuse xor gates jointly participated in phase detection, the reference spur generated by each xor gate neutralizes that generated from its complementary counterpart, without degrading the phase margin or incurring extra power. The high gain of the FXOR PD suppresses its noise contribution, and the PD inherently enables frequency tracking together with lock detection. Fabricated in a 130-nm SiGe BiCMOS process, the 80-GHz mmW PLL demonstrates a $-$ 73-dBc reference spur, a minimum integrated jitter of 79.5 fs $_{\mathrm{rms}}$ (10 kHz–100 MHz), and a figure of merit (FoM) of –241 dB.
- 30 September 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (1) , 59-70
Wideband and Efficient 256-GHz Subharmonic- Based FMCW Radar Transceiver in 130-nm SiGe BiCMOS Technology
This article proposes a fully integrated single-channel bistatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) that operates at a center frequency of 256 GHz. The main focus of this work is to realize a wideband and efficient radar TRX that offers high resolution of target detection in the short-range FMCW radar sensing application. The radar TRX chip is designed and manufactured using the 130 nm silicon – germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) technology which offers heterojunction bipolar transistors (HBTs) with $f_\mathbf{T}/f_\mathbf{MAX}$ of 300/500 GHz. The transmitter (TX) of the radar TRX is based on a fundamentally operated multiplier-by-8 chain architecture that offers a 3-dB bandwidth of around 65 GHz with a saturated output power of -5.4 dBm. On the other hand, the receiver (RX) is based on a subharmonic architecture that provides a conversion gain (CG) of 10.4 dB with an average noise figure (NF) of 23.5 dB. This TRX is realized with two integrated on-chip folded dipole antennas. The antenna offers high antenna gain and radiation efficiency due to the use of the selective localized backside etching (LBE) technique. This chip consumes 305 mW of power from a 3.3-V supply and occupies a silicon area of 3.3 mm $^2$ . The radar range measurement is performed in an anechoic chamber, and it shows the maximum dynamic range (DR) of around 34 dB at 1-m range of the target.
- 30 September 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 71 (1) , 59-70
Wideband and Efficient 256-GHz Subharmonic- Based FMCW Radar Transceiver in 130-nm SiGe BiCMOS Technology
This article proposes a fully integrated single-channel bistatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) that operates at a center frequency of 256 GHz. The main focus of this work is to realize a wideband and efficient radar TRX that offers high resolution of target detection in the short-range FMCW radar sensing application. The radar TRX chip is designed and manufactured using the 130 nm silicon – germanium (SiGe) bipolar complementary metal-oxide-semiconductor (BiCMOS) technology which offers heterojunction bipolar transistors (HBTs) with $f_\mathbf{T}/f_\mathbf{MAX}$ of 300/500 GHz. The transmitter (TX) of the radar TRX is based on a fundamentally operated multiplier-by-8 chain architecture that offers a 3-dB bandwidth of around 65 GHz with a saturated output power of -5.4 dBm. On the other hand, the receiver (RX) is based on a subharmonic architecture that provides a conversion gain (CG) of 10.4 dB with an average noise figure (NF) of 23.5 dB. This TRX is realized with two integrated on-chip folded dipole antennas. The antenna offers high antenna gain and radiation efficiency due to the use of the selective localized backside etching (LBE) technique. This chip consumes 305 mW of power from a 3.3-V supply and occupies a silicon area of 3.3 mm $^2$ . The radar range measurement is performed in an anechoic chamber, and it shows the maximum dynamic range (DR) of around 34 dB at 1-m range of the target.
- 22 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 70 (5) , 2642-2657
A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique
This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs rms at 40.96 GHz and 122 fs rms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW.
- 22 March 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 70 (5) , 2642-2657
A Low-Jitter and Low-Reference-Spur 320 GHz Signal Source With an 80 GHz Integer-N Phase-Locked Loop Using a Quadrature XOR Technique
This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs rms at 40.96 GHz and 122 fs rms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW.
- 16 January 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 38-40
Wideband, Compact and Efficient Frequency Quadrupler for Sub-Harmonic Transceiver in 130nm SiGe BiCMOS Technology
This paper proposes a compact and efficient frequency quadrupler (FQ) intended for a sub-harmonic transceiver. The circuit is based on stacked double bootstrapped Gilbert cell (GC) and works at the frequency band of 110-150GHz. It consists of two stacked mixing stages. The GC stages individually perform as a doubler for the input frequency, and the resultant quadrupled signal appears at the output of the second GC stage. The FQ achieves the peak conversion gain of 6.6dB and the maximum output power of -1dBm. The 3-dB bandwidth of this FQ is 40GHz(110-150GHz). Due to the compact design without compromising the performance, the stand-alone FQ Chip occupies only $0.056\text{mm}^{2}$ chip area and consumes only 13.4mA of current from the 3.3V supply. It achieves the maximum drain efficiency of 1.81%. The presented FQ is suitable for the frequency generation circuit in various system design applications above 100GHz.- 16 January 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 38-40
Wideband, Compact and Efficient Frequency Quadrupler for Sub-Harmonic Transceiver in 130nm SiGe BiCMOS Technology
This paper proposes a compact and efficient frequency quadrupler (FQ) intended for a sub-harmonic transceiver. The circuit is based on stacked double bootstrapped Gilbert cell (GC) and works at the frequency band of 110-150GHz. It consists of two stacked mixing stages. The GC stages individually perform as a doubler for the input frequency, and the resultant quadrupled signal appears at the output of the second GC stage. The FQ achieves the peak conversion gain of 6.6dB and the maximum output power of -1dBm. The 3-dB bandwidth of this FQ is 40GHz(110-150GHz). Due to the compact design without compromising the performance, the stand-alone FQ Chip occupies only $0.056\text{mm}^{2}$ chip area and consumes only 13.4mA of current from the 3.3V supply. It achieves the maximum drain efficiency of 1.81%. The presented FQ is suitable for the frequency generation circuit in various system design applications above 100GHz.- 1 January 2022
- Published by Springer Nature
- p. 845-867
Doppler Radar Sensor Platform
- 1 March 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Microwave and Wireless Components Letters
- Vol. 31 (5) , 497-500
A V-Band Low-Power Compact LNA in 130-nm SiGe BiCMOS Technology
This letter presents the design of a V-band low-power compact low-noise amplifier (LNA) in a 130-nm SiGe BiCMOS technology. For the low-power and low-noise requirements, transistors need to operate with low-voltage supply and low current density, which comes at the cost of lower gain per BJT stage. We use a technique to cancel the Miller capacitance in a single-stage differential amplifier and achieve high-gain, low-power, and low-noise simultaneously. The circuit topology is analyzed, and the transistor core layout and the matching network design considerations are discussed. The measured circuit shows a peak gain of 14.1 dB in a 3-dB bandwidth from 44 to 67 GHz while consuming 5.1 mW. Experimental results show an output power of 7.1 dBm at 1-dB compression with an associated power-added efficiency of 30%. The simulated noise figure is 3.3 dB at the center frequency. To the best of the authors' knowledge, the highest figure of merit among V-band LNAs based on silicon is reported.
- 1 March 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Microwave and Wireless Components Letters
- Vol. 31 (5) , 497-500
A V-Band Low-Power Compact LNA in 130-nm SiGe BiCMOS Technology
This letter presents the design of a V-band low-power compact low-noise amplifier (LNA) in a 130-nm SiGe BiCMOS technology. For the low-power and low-noise requirements, transistors need to operate with low-voltage supply and low current density, which comes at the cost of lower gain per BJT stage. We use a technique to cancel the Miller capacitance in a single-stage differential amplifier and achieve high-gain, low-power, and low-noise simultaneously. The circuit topology is analyzed, and the transistor core layout and the matching network design considerations are discussed. The measured circuit shows a peak gain of 14.1 dB in a 3-dB bandwidth from 44 to 67 GHz while consuming 5.1 mW. Experimental results show an output power of 7.1 dBm at 1-dB compression with an associated power-added efficiency of 30%. The simulated noise figure is 3.3 dB at the center frequency. To the best of the authors' knowledge, the highest figure of merit among V-band LNAs based on silicon is reported.
- 11 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 56 (3) , 899-913
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation
This article presents G-band monostatic and bistatic radar transceivers (TRX) incorporating on-chip antennas for short-range high-precision applications. The circuits were fabricated using a silicon-germanium (SiGe) BiCMOS technology offering heterojunction bipolar transistors (HBTs) with fT/fMAX of 300/500 GHz. The monostatic TRX implements a tunable leakage canceller (LC) for enhanced transmitter (TX)-to-receiver (RX) leakage compensation and hence improved detectability of weakly reflecting near targets. A standalone monostatic TRX characterized at on-wafer level achieves 4-dBm maximum output power (PTX) and 19-dB peak conversion gain (GRX) with 3-dB bandwidths of 18 and 17,GHz for the TX and the RX, respectively. The bistatic version reaches PTX of 13 dBm and GRX of 24 dB expanding the 3-dB bandwidths to 32 and 34 GHz for the TX and RX, respectively. A double-folded dipole antenna providing 5-dBi gain at 170 GHz was implemented using localized backside etching (LBE) and integrated with the transceivers. A frequency-modulated continuous-wave (FMCW) radar demonstrator incorporating an external phase-locked loop (PLL) was built to evaluate both TRXs and tunable leakage cancellation feature available in the monostatic variant. The maximum equivalent isotropic radiated power (EIRP), including on-chip antennas, is 8 and 18 dBm for the monostatic and bistatic TRX, respectively. The radars support sweep bandwidth up to 20 GHz reaching 2.1 cm spatial resolution. For a target at 1 m distance the measured ranging precision is 105 μm and 13 μm for monostatic and bistatic TRX, accordingly. Activation of leakage cancellation effectively suppresses close-in noise and extends the minimum detectable range remarkably.
- 11 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 56 (3) , 899-913
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation
This article presents G-band monostatic and bistatic radar transceivers (TRX) incorporating on-chip antennas for short-range high-precision applications. The circuits were fabricated using a silicon-germanium (SiGe) BiCMOS technology offering heterojunction bipolar transistors (HBTs) with fT/fMAX of 300/500 GHz. The monostatic TRX implements a tunable leakage canceller (LC) for enhanced transmitter (TX)-to-receiver (RX) leakage compensation and hence improved detectability of weakly reflecting near targets. A standalone monostatic TRX characterized at on-wafer level achieves 4-dBm maximum output power (PTX) and 19-dB peak conversion gain (GRX) with 3-dB bandwidths of 18 and 17,GHz for the TX and the RX, respectively. The bistatic version reaches PTX of 13 dBm and GRX of 24 dB expanding the 3-dB bandwidths to 32 and 34 GHz for the TX and RX, respectively. A double-folded dipole antenna providing 5-dBi gain at 170 GHz was implemented using localized backside etching (LBE) and integrated with the transceivers. A frequency-modulated continuous-wave (FMCW) radar demonstrator incorporating an external phase-locked loop (PLL) was built to evaluate both TRXs and tunable leakage cancellation feature available in the monostatic variant. The maximum equivalent isotropic radiated power (EIRP), including on-chip antennas, is 8 and 18 dBm for the monostatic and bistatic TRX, respectively. The radars support sweep bandwidth up to 20 GHz reaching 2.1 cm spatial resolution. For a target at 1 m distance the measured ranging precision is 105 μm and 13 μm for monostatic and bistatic TRX, accordingly. Activation of leakage cancellation effectively suppresses close-in noise and extends the minimum detectable range remarkably.
- 1 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 69 (1) , 1036-1047
Multimode W-Band and D-Band MIMO Scalable Radar Platform
This article demonstrates the implementation of 80- and 160-GHz four-channel radar sensors employing the modular scalable platform based on a single relaxed 40-GHz local oscillator and cascadable transceiver chips. The first two channels synthesize 2 x 2 multiple-input-multiple-output (MIMO) radar at 80 GHz with onboard 8 x 1 patch arrays for enhanced angular resolution, whereas the other two channels employ 160-GHz system-on-chip transceivers with integrated wideband 6-dBi micromachined on-chip antennas for enhanced range resolution. Configurable modulators in each transceiver offer ranging, direction-of-arrival (DoA) estimation, velocity/vibrations measurement, and data communication applications. Frequency-modulated continuous wave (FMCW) is demonstrated with 4-/8-GHz sweep bandwidth at 80/160 GHz corresponding to 3.75-/1.875-cm range resolution. Chirp-sequence FMCW is employed to measure the heartbeat rate of a human, and 78 bpm is measured with 0.06-Hz Doppler resolution. Mechanical vibration rate from a loudspeaker is measured using the CW radar technique, whereas phase-modulated continuous wave is employed for distant selective vibrations measurement. Time-division multiplexing MIMO radar is configured at 80 GHz in a multitarget scenario for DoA estimation, and the targets are distinguished with 25° effective angular resolution. Frequency-division multiplexing MIMO radar technique is demonstrated based on Δ Σ-modulation and binary phase shift keying (BPSK) modulators. Furthermore, the 10-Mb/s BPSK data communication link is evaluated at 80 GHz with a 20-dB signal-to-noise ratio at 1 m. The 160-GHz vector modulators offer additional modulations.
- 1 December 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 69 (1) , 1036-1047
Multimode W-Band and D-Band MIMO Scalable Radar Platform
This article demonstrates the implementation of 80- and 160-GHz four-channel radar sensors employing the modular scalable platform based on a single relaxed 40-GHz local oscillator and cascadable transceiver chips. The first two channels synthesize 2 x 2 multiple-input-multiple-output (MIMO) radar at 80 GHz with onboard 8 x 1 patch arrays for enhanced angular resolution, whereas the other two channels employ 160-GHz system-on-chip transceivers with integrated wideband 6-dBi micromachined on-chip antennas for enhanced range resolution. Configurable modulators in each transceiver offer ranging, direction-of-arrival (DoA) estimation, velocity/vibrations measurement, and data communication applications. Frequency-modulated continuous wave (FMCW) is demonstrated with 4-/8-GHz sweep bandwidth at 80/160 GHz corresponding to 3.75-/1.875-cm range resolution. Chirp-sequence FMCW is employed to measure the heartbeat rate of a human, and 78 bpm is measured with 0.06-Hz Doppler resolution. Mechanical vibration rate from a loudspeaker is measured using the CW radar technique, whereas phase-modulated continuous wave is employed for distant selective vibrations measurement. Time-division multiplexing MIMO radar is configured at 80 GHz in a multitarget scenario for DoA estimation, and the targets are distinguished with 25° effective angular resolution. Frequency-division multiplexing MIMO radar technique is demonstrated based on Δ Σ-modulation and binary phase shift keying (BPSK) modulators. Furthermore, the 10-Mb/s BPSK data communication link is evaluated at 80 GHz with a 20-dB signal-to-noise ratio at 1 m. The 160-GHz vector modulators offer additional modulations.