Bilal Akin
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Bilal Akin has a total of 130 co-authors. Here are the top co-authors by number of shared publications:
- Fei Yang
Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA
20 shared publications - Enes Ugur
Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, USA
13 shared publications - Shi Pu
Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX, 75080, USA
12 shared publications - Bhanu Teja Vankayalapati
The University of Texas at Dallas, Richardson, TX, USA
10 shared publications - Masoud Farhadi
Texas Instruments Inc., Dallas, TX, USA
9 shared publications - Mojtaba Afshar
University of Texas at Dallas, Richardson, TX, USA
9 shared publications
Latest Publications
- 3 March 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (9) , 14792-14807
Robust HFI-Based Sensorless Control of SMPMSMs in the Presence of Large Position Estimation Errors
Due to the inherently low saliency of SMPMSMs, achieving stable high-load operation with HFI-based sensorless control at startup or low speeds is challenging. Moreover, even small cross-saturation inductances can cause significant errors in the estimated rotor angle. This paper proposes a physics-informed strategy that adjusts the $d$-axis reference current to ensure a minimum saliency while running FOC with the estimated angle, without explicit angle compensation. Positive $I_{d}$ injection intentionally saturates the motor, reducing inductances and creating sufficient saliency for stable HFI operation. The method defines the minimum $I_{d}$ for maximum torque operation, ensures accurate torque tracking across the full torque range, and provides an initial position detection (IPD) scheme that eliminates the need for a polarity check. Resonant controllers are incorporated to mitigate inverter nonlinearities and spatial harmonic effects, reducing speed and angle ripple. Experiments on a 400 W SMPMSM demonstrate reliable low-speed operation, startup under load, smooth transitions to a B-emf observer, and robust performance under varying torque conditions, validating the effectiveness and practical applicability of the proposed approach, which is also mathematically formulated and rigorously analyzed.
- 3 March 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (9) , 14792-14807
Robust HFI-Based Sensorless Control of SMPMSMs in the Presence of Large Position Estimation Errors
Due to the inherently low saliency of SMPMSMs, achieving stable high-load operation with HFI-based sensorless control at startup or low speeds is challenging. Moreover, even small cross-saturation inductances can cause significant errors in the estimated rotor angle. This paper proposes a physics-informed strategy that adjusts the $d$-axis reference current to ensure a minimum saliency while running FOC with the estimated angle, without explicit angle compensation. Positive $I_{d}$ injection intentionally saturates the motor, reducing inductances and creating sufficient saliency for stable HFI operation. The method defines the minimum $I_{d}$ for maximum torque operation, ensures accurate torque tracking across the full torque range, and provides an initial position detection (IPD) scheme that eliminates the need for a polarity check. Resonant controllers are incorporated to mitigate inverter nonlinearities and spatial harmonic effects, reducing speed and angle ripple. Experiments on a 400 W SMPMSM demonstrate reliable low-speed operation, startup under load, smooth transitions to a B-emf observer, and robust performance under varying torque conditions, validating the effectiveness and practical applicability of the proposed approach, which is also mathematically formulated and rigorously analyzed.
- Open Access
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of Power Electronics
- Vol. 7, 2464-2497
Saturation and Active Region Operation of SiC MOSFETs and Si-IGBTs: A State-of-the-Art Review and Future Directions
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of Power Electronics
- Vol. 7, 2464-2497
Open AccessSaturation and Active Region Operation of SiC MOSFETs and Si-IGBTs: A State-of-the-Art Review and Future Directions
- 24 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Industrial Electronics
- Vol. 7 (1) , 46-57
Optimal Feature Selection for Distributed Bearing Fault Detection Using Cost-Effective, High-Performance Machine Learning Algorithms
This study presents a highly accurate and cost-efficient machine learning framework for diagnosing distributed bearing faults by identifying an optimal and compact set of frequency-domain features. The analysis is based on a comprehensive dataset collected from an experimental testbed comprising a coupled induction motor operating under 50 distinct combinations of speed and load. The dataset encompasses both healthy bearings and those exhibiting various distributed faults-such as lubrication degradation, contamination, electrical erosion, and flaking-as well as a localized fault in the form of a single-point defect on the outer race. Data were acquired using a multi-sensor module integrating three-axis vibration, stray magnetic flux, and two phase current signals. The primary objective is to reduce an initial set of 102 frequency-based features to a minimal subset suitable for deployment on resource-constrained microcontrollers without sacrificing classification performance. Employing Mutual Information and Random Forest techniques for feature selection, the study successfully identifies a critical subset of five features. A Random Forest classifier trained on these features achieved an impressive test accuracy of 99.58%. Furthermore, the combination of top-ranked features from both MI and RF methods led to improved classification performance over using either method independently, thereby enhancing the robustness and reliability of industrial bearing fault detection.
- 24 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Industrial Electronics
- Vol. 7 (1) , 46-57
Optimal Feature Selection for Distributed Bearing Fault Detection Using Cost-Effective, High-Performance Machine Learning Algorithms
This study presents a highly accurate and cost-efficient machine learning framework for diagnosing distributed bearing faults by identifying an optimal and compact set of frequency-domain features. The analysis is based on a comprehensive dataset collected from an experimental testbed comprising a coupled induction motor operating under 50 distinct combinations of speed and load. The dataset encompasses both healthy bearings and those exhibiting various distributed faults-such as lubrication degradation, contamination, electrical erosion, and flaking-as well as a localized fault in the form of a single-point defect on the outer race. Data were acquired using a multi-sensor module integrating three-axis vibration, stray magnetic flux, and two phase current signals. The primary objective is to reduce an initial set of 102 frequency-based features to a minimal subset suitable for deployment on resource-constrained microcontrollers without sacrificing classification performance. Employing Mutual Information and Random Forest techniques for feature selection, the study successfully identifies a critical subset of five features. A Random Forest classifier trained on these features achieved an impressive test accuracy of 99.58%. Furthermore, the combination of top-ranked features from both MI and RF methods led to improved classification performance over using either method independently, thereby enhancing the robustness and reliability of industrial bearing fault detection.
- 25 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Power Electronics
- Vol. 14 (2) , 2035-2048
Analysis and Design of a Resistor-Less DC-Bus Active Discharge and Dynamic Braking Scheme Using IGBTs in the Active Region
During shutdowns, emergency conditions, and dynamic braking, fully discharging the dc-bus capacitor or clamping the dc-bus voltage in industrial systems is typically managed using power resistors and additional switches. This conventional approach increases system cost, size, and complexity. This paper introduces a compact, cost-effective, resistor-less method for two functions: (a) active discharge and (b) dynamic braking in low-power industrial systems. The proposed technique operates IGBTs in their active region with low gate-emitter voltages (VGE), creating high impedance in the discharge path to limit current. For active discharge, a constant-power strategy is implemented using pulse frequency modulation (PFM), where the on-time (ton) of each pulse is fixed and the pulse frequency is ramped up to accelerate energy dissipation. This approach enables complete discharge of a 600 V dc-bus within 1 second, handled entirely by a single IGBT. The method is validated across three different IGBT vendors, showing consistent results and long-term reliability with no parameter degradation after over 200,000 completed discharge cycles. For dynamic braking, the PFM method with fixed pulse frequency enables continuous power dissipation between 50 W and 150 W for over 30 minutes. It effectively replaces conventional internal braking resistors typically rated from 20 W to 200 W with resistance values of 5-120 Ω. The system can also tolerate brief overloads up to 50% beyond IGBT current ratings for 10-20 seconds, providing sufficient time to complete braking without failure, as confirmed by test results. All these benefits are achieved through a simple gate driver modification that supplies partial VGE levels (3-10 V), eliminating bulky resistors, reducing cost by at least 50%, and saving space-making the solution ideal for high-volume industrial applications.
- 25 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Power Electronics
- Vol. 14 (2) , 2035-2048
Analysis and Design of a Resistor-Less DC-Bus Active Discharge and Dynamic Braking Scheme Using IGBTs in the Active Region
During shutdowns, emergency conditions, and dynamic braking, fully discharging the dc-bus capacitor or clamping the dc-bus voltage in industrial systems is typically managed using power resistors and additional switches. This conventional approach increases system cost, size, and complexity. This paper introduces a compact, cost-effective, resistor-less method for two functions: (a) active discharge and (b) dynamic braking in low-power industrial systems. The proposed technique operates IGBTs in their active region with low gate-emitter voltages (VGE), creating high impedance in the discharge path to limit current. For active discharge, a constant-power strategy is implemented using pulse frequency modulation (PFM), where the on-time (ton) of each pulse is fixed and the pulse frequency is ramped up to accelerate energy dissipation. This approach enables complete discharge of a 600 V dc-bus within 1 second, handled entirely by a single IGBT. The method is validated across three different IGBT vendors, showing consistent results and long-term reliability with no parameter degradation after over 200,000 completed discharge cycles. For dynamic braking, the PFM method with fixed pulse frequency enables continuous power dissipation between 50 W and 150 W for over 30 minutes. It effectively replaces conventional internal braking resistors typically rated from 20 W to 200 W with resistance values of 5-120 Ω. The system can also tolerate brief overloads up to 50% beyond IGBT current ratings for 10-20 seconds, providing sufficient time to complete braking without failure, as confirmed by test results. All these benefits are achieved through a simple gate driver modification that supplies partial VGE levels (3-10 V), eliminating bulky resistors, reducing cost by at least 50%, and saving space-making the solution ideal for high-volume industrial applications.
- 12 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (2) , 1677-1689
A DHTOL Test-Based Methodology to Investigate the Switching Reliability of GaN HEMTs Under Repeated Drain Voltage Ringing
The dynamic high-temperature operating lifetime (DHTOL) test is used to validate the product level robustness of a device in interaction with other system components and various product operating modes. This article presents a DHTOL-based test methodology for investigating the switching reliability of gallium nitride high electron mobility transistors in applications involving large drain-to-source voltage ringing. To conduct this study, a highly scalable, modular and reconfigurable test bench architecture is presented that can simultaneously test multiple devices under realistic stress conditions. The test vehicles are designed to replicate the switching stress typical of a quasi-resonant flyback converter while optimizing overall power consumption. In addition, the setup includes features for inline dynamic $R_{DS,\text{ON}}$ monitoring, enabling user-friendly tracking of the changes of this key parameter throughout the test duration. This real-time monitoring capability is highly beneficial for understanding and gaining valuable insights into the evolution of the devices’ $R_{DS,\text{ON}}$ under continuous stress conditions. Using a prototype of the proposed test bench, multiple samples from three different device vendors are stressed under two distinct test conditions each. All tests are conducted over an intended duration of 1000 h and a detailed description of the results observed is also presented in this article.
- 12 August 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 41 (2) , 1677-1689
A DHTOL Test-Based Methodology to Investigate the Switching Reliability of GaN HEMTs Under Repeated Drain Voltage Ringing
The dynamic high-temperature operating lifetime (DHTOL) test is used to validate the product level robustness of a device in interaction with other system components and various product operating modes. This article presents a DHTOL-based test methodology for investigating the switching reliability of gallium nitride high electron mobility transistors in applications involving large drain-to-source voltage ringing. To conduct this study, a highly scalable, modular and reconfigurable test bench architecture is presented that can simultaneously test multiple devices under realistic stress conditions. The test vehicles are designed to replicate the switching stress typical of a quasi-resonant flyback converter while optimizing overall power consumption. In addition, the setup includes features for inline dynamic $R_{DS,\text{ON}}$ monitoring, enabling user-friendly tracking of the changes of this key parameter throughout the test duration. This real-time monitoring capability is highly beneficial for understanding and gaining valuable insights into the evolution of the devices’ $R_{DS,\text{ON}}$ under continuous stress conditions. Using a prototype of the proposed test bench, multiple samples from three different device vendors are stressed under two distinct test conditions each. All tests are conducted over an intended duration of 1000 h and a detailed description of the results observed is also presented in this article.
- 18 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40 (11) , 16512-16524
An Active Discharge Scheme for DC-Bus Capacitors in EV Powertrain
During the emergency situations, key-OFFs, or maintenance, discharging the inverter dc-bus capacitor voltage within seconds is imperative due to safety concerns (inverter not used to control motor). Conventional discharge methods rely on external resistors, additional switches, or motor windings, increasing cost, space requirements, and control complexity. This article presents a cost-effective and space-efficient solution that enables fast capacitor discharge by operating the inverter’s SiC mosfets-either discrete devices or power modules-in linear mode. The proposed method utilizes a constant power tracking approach with pulse frequency modulation to safely discharge the high-voltage bus capacitor without external components. When the car is off, the proposed scheme discharges a 1000-V dc bus within 1 s using a single low-side SiC switch to test a worst-case scenario. In practice, all six devices can be used to share thermal stress, and the discharge time can be extended to 5 s as suggested by safety standards. Optimal operating conditions, including gate-source voltage $(V_{GS})$ and pulse width $(t_{\textsc{{ON}}})$, are identified for different mosfets from various vendors. To assess long-term reliability, devices undergo more than 200 000 discharge cycles, with intrinsic parameter monitoring and failure analysis conducted to determine degradation mechanisms. The findings help establish safe operating conditions, ensuring robust and reliable integration of the proposed discharge method within the main powertrain inverter.
- 18 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Power Electronics
- Vol. 40 (11) , 16512-16524
An Active Discharge Scheme for DC-Bus Capacitors in EV Powertrain
During the emergency situations, key-OFFs, or maintenance, discharging the inverter dc-bus capacitor voltage within seconds is imperative due to safety concerns (inverter not used to control motor). Conventional discharge methods rely on external resistors, additional switches, or motor windings, increasing cost, space requirements, and control complexity. This article presents a cost-effective and space-efficient solution that enables fast capacitor discharge by operating the inverter’s SiC mosfets-either discrete devices or power modules-in linear mode. The proposed method utilizes a constant power tracking approach with pulse frequency modulation to safely discharge the high-voltage bus capacitor without external components. When the car is off, the proposed scheme discharges a 1000-V dc bus within 1 s using a single low-side SiC switch to test a worst-case scenario. In practice, all six devices can be used to share thermal stress, and the discharge time can be extended to 5 s as suggested by safety standards. Optimal operating conditions, including gate-source voltage $(V_{GS})$ and pulse width $(t_{\textsc{{ON}}})$, are identified for different mosfets from various vendors. To assess long-term reliability, devices undergo more than 200 000 discharge cycles, with intrinsic parameter monitoring and failure analysis conducted to determine degradation mechanisms. The findings help establish safe operating conditions, ensuring robust and reliable integration of the proposed discharge method within the main powertrain inverter.
- 15 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Packaging and Manufacturing Technology
- Vol. 15 (8) , 1732-1740
Gate Oxide and Package Reliability of TO-263 SiC MOSFETs
This paper presents a comprehensive reliability analysis of TO-263 silicon carbide MOSFETs (SiC MOSFETs) from four different vendors, focusing on gate oxide and package degradation. A range of accelerated aging tests (AATs), including positive high-temperature gate bias (PHTGB), negative high-temperature gate bias (NHTGB), high-temperature reverse bias (HTRB), and DC power cycling (DCPC), are conducted to investigate both gate oxide and package reliability. The findings from HTGB and HTRB tests emphasize that even a 10 nm reduction in gate oxide thickness can significantly impact gate oxide reliability compared to similar designs. Furthermore, the results from NHTGB show that the devices are more prone to failure compared to PHTGB, disproving the idea that the device lifetime is longer in the off-state compared to the on-state. The conclusions are drawn from measurements using focused ion beam (FIB) and transmission electron microscopy (TEM), which provide detailed cross-sectional images of the devices. Additionally, the reliability of the TO-263 package is assessed, highlighting solder fatigue failure between the device and the printed circuit board (PCB) as a significant issue. This failure mechanism can lead to the detachment of the device from the PCB, resulting in a loss of connection. The study underscores the importance of optimizing gate oxide thickness and addressing thermal-mechanical stresses to enhance the overall reliability of SiC MOSFETs with TO-263 packages in high-power applications.
- 15 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Packaging and Manufacturing Technology
- Vol. 15 (8) , 1732-1740
Gate Oxide and Package Reliability of TO-263 SiC MOSFETs
This paper presents a comprehensive reliability analysis of TO-263 silicon carbide MOSFETs (SiC MOSFETs) from four different vendors, focusing on gate oxide and package degradation. A range of accelerated aging tests (AATs), including positive high-temperature gate bias (PHTGB), negative high-temperature gate bias (NHTGB), high-temperature reverse bias (HTRB), and DC power cycling (DCPC), are conducted to investigate both gate oxide and package reliability. The findings from HTGB and HTRB tests emphasize that even a 10 nm reduction in gate oxide thickness can significantly impact gate oxide reliability compared to similar designs. Furthermore, the results from NHTGB show that the devices are more prone to failure compared to PHTGB, disproving the idea that the device lifetime is longer in the off-state compared to the on-state. The conclusions are drawn from measurements using focused ion beam (FIB) and transmission electron microscopy (TEM), which provide detailed cross-sectional images of the devices. Additionally, the reliability of the TO-263 package is assessed, highlighting solder fatigue failure between the device and the printed circuit board (PCB) as a significant issue. This failure mechanism can lead to the detachment of the device from the PCB, resulting in a loss of connection. The study underscores the importance of optimizing gate oxide thickness and addressing thermal-mechanical stresses to enhance the overall reliability of SiC MOSFETs with TO-263 packages in high-power applications.