Jae Kyeong Jeong

Amorphous InGaZnO has long served as the foundational material for display backplanes. Nonetheless, the escalating demand for ultra-high resolution and reduced power consumption necessitates higher-performance oxide thin-film transistors (TFTs) capable of replacing polycrystalline silicon and enabling fully oxide-based TFT architectures. Crystallization of oxide semiconductors offers a promising route toward higher carrier mobility, yet achieving highly ordered oxide channels on amorphous substrates remains challenging. Herein, we report an electrode-induced lateral crystallization (EILC) method that exploits crystallographic coherence and lattice matching between the electrode and oxide channel to enable formation of highly oriented, large-grained InGaO at a modest temperature of 400 °C. The resultant EILC TFTs exhibit unprecedented electrical characteristics and exceptional bias-stress stability. Structural analyses indicate that crystallographic coherence between the indium tin oxide electrode and the channel, rather than interfacial redox reactions, governs this process, positioning EILC as a paradigm-shifting strategy for next-generation oxide electronics.

Precise control of the subthreshold swing (SS) in pixel-driving thin-film transistors (TFTs) is critical for accurate gray-scale expression and stable analog current modulation in active-matrix displays. Here, we demonstrate deterministic SS engineering in amorphous indium–gallium oxide (a-IGO) TFTs by controlling the vertical position of a tin (Sn) δ-doped layer within the oxide channel using plasma-enhanced atomic layer deposition. Sn δ-doped layers were selectively inserted near the passivation side, at the middle of the channel, and near the gate-insulator interface, while the macroscopic structural and chemical properties of the channel films remained nearly identical. Despite this structural similarity, the electrical characteristics were systematically modulated solely by the spatial location of the Sn layer. As the Sn δ-doped layer approached the front-channel conduction path, the SS increased from 0.128 to 0.462 V/decade, accompanied by a positive threshold-voltage shift from 0.03 to 0.99 V and a decrease in field-effect mobility from 36.5 to 19.3 cm2/V·s. Energy-band analyses indicate that these position-dependent electrical variations originate from the different degrees of interaction between Sn2+-induced trap centers and the bending quasi-Fermi level during subthreshold operation. This spatial trap-interaction model was further supported by frequency-dependent capacitance–voltage measurements, which revealed more pronounced frequency dispersion and stretch-out behavior when the Sn δ-doped layer was located closer to the front channel. Importantly, the Sn δ-doped TFTs exhibited bias-stress reliability comparable to that of the pristine IGO reference, with threshold-voltage shifts no greater than 0.60 V under the tested conditions. The capture and emission kinetics of the states associated with the Sn2+-related SS modulation remain to be established. These results establish vertically positioned Sn δ-doping as an effective and reliable strategy for tailoring the SS of amorphous oxide TFTs, providing a useful device-design pathway for OLED pixel-driving circuits that require precise current modulation and improved low-gray-level uniformity.

Amorphous indium gallium zinc oxide thin‐film transistors are widely used in high‐end organic light‐emitting diode displays. However, their intrinsic mobility–stability trade‐off fundamentally limits further performance scaling. Crystallized oxide semiconductors have emerged as a promising pathway to overcome this constraint, yet the relative roles of crystallinity and crystallographic alignment remain unclear. Here, we systematically compare amorphous, random‐polycrystalline, and highly aligned crystalline indium gallium oxide channels to elucidate the origin of enhanced charge transport. Temperature‐dependent electrical analysis and multi‐frequency capacitance–voltage spectroscopy reveal that crystallographic alignment sharpens and energetically stabilizes subgap states near the conduction band, indicating reduced energetic disorder. Spatially resolved potential analysis further shows that this alignment suppresses grain‐boundary‐induced potential barriers, producing a more uniform transport landscape. In contrast, random‐polycrystalline channels retain broadened subgap states and spatially distributed grain‐boundary barriers despite their crystallinity. These results show that crystallographic alignment, rather than crystallinity alone, governs charge transport in polycrystalline oxide semiconductors by concurrently optimizing the energetic and spatial aspects of the electronic landscape, while maintaining robust bias‐stress stability.

Spacer-defined offset engineering is presented as a structural strategy to enhance the on-state current (ION) of vertical gate-all-around (VGAA) amorphous indium–gallium oxide (IGO) field-effect transistors (FETs) while preserving threshold-voltage (VTH) control. Increasing the indium fraction in the IGO channel improved ION but simultaneously caused a pronounced negative VTH shift, revealing an observed trade-off in composition-based channel engineering. To circumvent this limitation, the SiO2 spacer thickness was scaled from 100 to 30 nm while maintaining the optimized IGO 6:3 channel composition. For IGO FETs with a gate length of 40 nm, the average ION increased from 1.24 ± 0.54 to 9.5 ± 1.94 μA as the spacer thickness was reduced from 100 to 30 nm, without inducing a negative VTH shift. For twenty 30-nm-spacer devices, the average VTH and subthreshold swing were 0.29 ± 0.05 V and 71.4 ± 4 mV/dec, respectively, with an apparent drain-induced barrier lowering (DIBL) factor of 3.7 mV/V. Y-function analysis, temperature-dependent measurements, and Technology Computer-Aided Design (TCAD) simulations revealed that the performance enhancement originated from reduced access resistance and electrostatic modulation of the source-side access region, while no statistically distinct spacer-dependent change in the effective source-side injection barrier was resolved. The optimized device also exhibited VTH shifts of only +79 and –26 mV under positive and negative bias-temperature stress, respectively, at 95 °C for 3600 s under effective gate fields of ±3 MV/cm, while the VGAA-based two-transistor zero-capacitor dynamic random-access memory (2T0C DRAM) cell exhibited a retention time exceeding 100 s. These results establish spacer-defined offset engineering as an effective structural design approach for oxide-semiconductor memory transistors that require both high ION and stable VTH operation.

As conventional silicon-based dynamic random-access memory (DRAM) approaches its physical and electrical scaling limits, oxide semiconductors have emerged as promising channel materials for next-generation memory devices because of their low off-state current and process compatibility. Among them, indium gallium oxide (IGO) thin-film transistors (TFTs) have attracted considerable attention for DRAM-related applications; however, their implementation remains challenging because the device stack must withstand high-thermal-budget back-end-of-line processing, including annealing at 600 °C in a N2 ambient which can promote oxygen-deficient conditions in oxide layers. Here, we systematically investigate the effects of passivation-layer selection on the electrical performance and thermal reliability of IGO TFTs by comparing Al2O3-, HfO2-, and SiO2-passivated devices before and after 600 °C N2 annealing. Among the passivation layers examined, Al2O3 uniquely preserved stable transistor operation after the high-temperature process, whereas the HfO2- and SiO2-passivated devices exhibited severe degradation of switching behavior and became electrically unextractable after 10 min annealing. In contrast, the Al2O3-passivated TFTs retained excellent electrical characteristics, including a field-effect mobility of 94.08 cm2V–1s–1 and a subthreshold swing of 84 mVdec–1 after 10 min annealing. Moreover, the positive-bias temperature stress stability was markedly improved, with the threshold-voltage shift at 100 °C decreasing from 63 to 20 mV after extended annealing. The superior reliability of Al2O3 layer may be attributed to its strong Al–O bonding and high film density, which provide enhanced chemical and structural stability during high-temperature N2 annealing. These findings suggest that Al2O3 passivation is an effective strategy for enabling thermally robust and electrically reliable IGO TFTs for advanced DRAM applications.

Data‐intensive workloads demand energy‐efficient platforms that seamlessly integrate memory, processing, and spatiotemporal responses. Oxide transistors offer a compelling route toward this goal due to their low‐temperature processability, large‐area uniformity, low off‐state leakage, and defect‐mediated temporal dynamics. In this review, we discuss oxide‐transistor‐based neuromorphic devices from the perspectives of materials physics, device operation, and hardware implementation. We first outline how wide‐bandgap electronic structures, oxygen‐related defects, cation chemistry, carrier transport, and stress‐induced instabilities govern the electrical and optoelectronic responses of oxide semiconductors. We then examine synaptic devices based on charge trapping, ferroelectric polarization, and light‐induced conductance modulation, highlighting how those mechanisms enable multilevel weight storage, short‐ and long‐term plasticity, timing‐dependent learning, and artificial vision functions. Finally, we discuss the transition from device‐level synaptic emulation to practical neuromorphic hardware, emphasizing conductance linearity, retention, variability, array addressability, in‐memory computing, and in‐sensor processing. Oxide neuromorphic devices require that defects and transient dynamics be controlled as functional resources, not eliminated as reliability concerns. This perspective positions oxide transistors not merely as artificial synapse elements, but as multifunctional device platforms in which memory, sensing, and computation can be combined through controlled material dynamics.

Intelligent systems operate in environments where multiple physical stimuli coexist and interact, yet most optoelectronic synaptic devices have primarily been limited to single‐modal operation. This review expands optoelectronic synapses beyond conventional optical‐electrical modulation toward a multisensory neuromorphic framework that incorporates thermal, mechanical, chemical, acoustic, and other physical stimuli. In multimodal optoelectronic synaptic systems, sensing, memory, and computation are coupled through conductance‐state evolution. External stimuli perturb internal variables such as photocarrier density, trap occupancy, ion distribution, interfacial polarization, adsorption‐induced charge, or phase state. The resulting changes in these internal states modulate conductance, producing volatile responses for transient sensory encoding or nonvolatile states for memory storage and weighted readout. We systematically review multimodal plasticity in optoelectronic synapses from both mechanism‐oriented and architecture‐based perspectives. Fundamental mechanisms are classified into five types: molecular structural transformation, filamentary switching, band structure engineering, field‐induced charge modulation, and carrier generation pathways. In this review, the reported multimodal optoelectronic neuromorphic devices are classified into five architectural types according to where transduction, memory, and computation occur, including single‐device integration, parallel multimodal processing, sensor‐coupled preprocessing, cross‐modal conversion, and stimulus‐dependent bidirectional plasticity. Representative applications in pattern recognition, adaptive learning, and in‐sensor/in‐memory computing are discussed as fundamental demonstrations toward realizing hardware‐level multisensory intelligence.

Monolithic three-dimensional (3D) integration—collocating logic and memory in the back-end-of-line (BEOL)—offers higher bandwidth, lower latency, and improved energy efficiency for AI, cloud, and edge systems. Pairing two-dimensional p-type semiconductors with oxide n-channel transistors establishes a practical basis for complementary BEOL CMOS. This Review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle p-doping, and mitigation of crystallization, volatility, and interdiffusion. Recent gain-cell and vertical complementary field-effect transistor (CFET) demonstrations are examined, and a pragmatic outlook for BEOL p-type 2D semiconductors is outlined toward manufacturable, dense, low-power monolithic 3D chips.