James W. Pomeroy

Thermal properties of quasi-vertical GaN-on-sapphire p–n diodes and fully vertical GaN-on-tungsten (W) p–n diodes were investigated. Fully vertical GaN-on-W devices were realized by transferring GaN membranes from sapphire substrates via a laser lift-off process and bonding to a metallic tungsten substrate. Device temperatures were measured using micro-Raman thermography with surface-deposited TiO2 nanoparticles acting as thermometers, and the thermal resistance was determined from the measurement results by 3D thermal simulations. Fully vertical GaN-on-W diodes showed a 3.1× reduction in device thermal resistance compared to quasi-vertical GaN-on-sapphire diodes (21.1 ± 1.5 to 6.8 ± 0.4 mK cm2/W). The extracted thermal resistance is close to simulated models of GaN-on-GaN p–n diodes, validating tungsten as an excellent, thermally stable metallic substrate for GaN-based high-power vertical devices.

Hot electrons in polarization-graded AlGaN/GaN high electron mobility transistors (HEMTs) were investigated using electroluminescence (EL) spectroscopy and compared to reference conventional abrupt-interface HEMTs. The electron temperature Te was determined from EL over a range of bias voltages and ambient temperatures. Te was lower for the polarization-graded devices, with a Te saturation observed at drain voltage VDS>13 V. Hydrodynamic technology computer-aided design (TCAD) simulations, calibrated to experimental IV and Te data, show that a 24% reduction in the peak lateral electric field is the primary driver for the reduced Te in the polarization-graded HEMTs. Electric field and hot carrier effects are clearly reduced in polarization-graded devices, with potential implications for improved reliability and noise performance. A consistent hot electron relaxation time of 18 fs was determined for both device types, demonstrating further that EL-based measurements are a powerful tool for calibrating TCAD models and probing hot carriers in GaN transistors.

AlGaN/GaN multi-channel Super Lattice Castellated Field Effect Transistors (SLCFETs) have shown great potential for next generation RF applications. We demonstrate a 2.44× reduction in thermal resistance reduction in AlGaN/GaN multi-channel SLCFETs by replacing the standard AlGaN buffer with a high thermal conductivity AlN buffer layer and adding a poly-crystalline diamond overcoat layer. The thermal conductivity of each material in the device stack was measured using time-domain and frequency-domain thermoreflectance techniques, including 223⁺²¹₋₁₈ W/m·K for 2.2 μm-thick AlN buffer versus 38^+5.5₋₅ W/m·K for the reference 1.8 μm AlGaN buffer. Device thermal resistance was reduced from 29 mm°C/W to 11.9 mm°C/W by combining the AlN buffer and poly-crystalline diamond overcoat layer, determined using Raman thermography together with 3-D thermal simulation. The corresponding 2.44× increase RF power density capability enabled by improved thermal management can unlock the next-generation ultra-high-power RF devices.

The thermal characteristics of large area GaN HEMTs on 200 mm QST engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST substrates are extracted through Raman thermography combined with 3-D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST is up ~1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.

We provide direct evidence of two-dimensional hole gas (2DHG) conduction occurring in parallel with the two-dimensional electron gas (2DEG) channel in AlN/GaN/AlN high-electron-mobility transistors, using combined electrical characterization and electric-field-induced second harmonic generation. Anomalous OFF-state leakage and diode-like field distributions, which are also confirmed in isolation structures where the top heterostructures along with the 2DEG channel have been etched, reveal a buried leakage path mediated by the 2DHG. This leakage arises from Fowler–Nordheim tunneling with electron–hole pairs generation under the gate, which activates a vertical 2DEG–2DHG diode-like pathway, and from Poole–Frenkel transport that connects the 2DHG to the ohmic contacts. An equivalent circuit model is proposed to describe these mechanisms. The upper bound of the buried 2DHG sheet resistance is estimated to be 10 MΩ/sq, while the vertical resistance between the 2DHG and n++GaN is 35 MΩ mm. These findings provide a direct visualization and a comprehensive model of 2DHG-mediated leakage, offering design strategies to suppress parasitic conduction and improve device performance.

This study presents a comprehensive thermal analysis of GaN/3C-SiC/diamond high-electron-mobility transistors (HEMTs), focusing on optimizing heat dissipation through a novel integration of nanosecond transient thermoreflectance (ns-TTR) and Raman thermography. By applying these techniques to fully fabricated devices, we directly measured layer-specific thermal conductivities and boundary resistances using the preexisting gate electrode as the transducer, enabling in situ characterization of thermal properties. Finite element simulations, using ns-TTR-measured parameters and validated by experimental temperature profiles, revealed an optimal thickness-dependent trade-off range in GaN thermal conductivity. These insights provide a framework for designing high-power-density HEMTs with balanced thermal and structural performance, emphasizing the need to optimize GaN thickness and transition layer (TL) properties for efficient heat management.

Diamond is an attractive substrate choice for the growth of gallium oxide for high-power device applications due to its high thermal conductivity. However, the cubic crystal structure of diamond is very different from that of monoclinic β-Ga2O3. Adding to the complexity, there is a large surface energy difference between the two materials, and a high-temperature oxide environment is required for Ga2O3 growth. Here, we demonstrate a viable pathway that enables thick adherent Ga2O3 layers to be grown epitaxially on diamond (001) substrates, using metal–organic chemical vapor deposition. This growth is achieved using an intermediary (Al0.06Ga0.94)2O3 (AGO6) buffer layer. Omission of the strain management buffer results in Ga2O3 films that exfoliate into membranes for thicknesses greater than about 500 nm. Implementation of the buffer layer allows for the alleviation of the excess strain energy developed within the grown film and assists in improving film quality, increasing grain size, reducing dislocations, and providing epitaxially textured thin films relative to layers without the buffer. Adherent 750-nm-thick β-Ga2O3 epitaxial layers have been achieved using the AGO6 buffer, with a full-width at half-maximum of 1.36° and a root-mean-square roughness of 6.24 nm. The thermal conductivity of the β-Ga2O3 thin films with and without the AGO6 buffer was measured to be 6.0–6.5 W/mK. Thus, integration of the monoclinic gallium oxide with the diamond cubic substrate using the intermediary buffer layer improves the crystal quality but does not impact the thermal conductivity, suggesting the future feasibility of using diamond substrates for a wide range of Ga2O3 device applications.

Aluminium gallium nitride/gallium nitride (AlGaN/GaN)-based superlattice castellated field-effect transistors are a potential basis for high-power radiofrequency amplifiers and switches in future radars. The reliability of such devices, however, is not well understood. Here we report transistor latching in multichannel GaN transistors. At the latching condition, drain current sharply transits from an off-state value to a high on-state value with a slope less than 60 mV per decade. Current–voltage measurements, simulations and correlated electroluminescent emission at the latching condition indicate that triggering of fin-width-dependent localized impact ionization is responsible for the latching. This localization is attributed to the presence of fin-width variation due to variability in the fabrication process. The latching condition is reversible and non-degrading, and we show that it can lead to improvement in the transconductance characteristics of transistors, implying improved linearity and power in radiofrequency power amplifiers.

Incorporation of low aluminum composition AlGaN buffer layers mitigates short channel effects in high-frequency GaN HEMTs. However, there is a trade-off between improved carrier confinement and increased thermal resistance of the AlGaN buffer. This work investigates the impact of the thermal conductivity of AlGaN back barriers on the overall thermal resistance of RF HEMTs. Nanosecond time-domain thermoreflectance is used to measure the thermal conductivity of GaN and Al_xGa_1-xN in the range of x = 0.01 to 0.06. The room temperature thermal conductivity decreased from 39 W/m·K to 19 W/m·K for x = 0.01 and 0.06 respectively, which is considerably lower than the 145 W/m·K measured for GaN. Notably, the Callaway model underpredicts the AlGaN thermal conductivity reduction in the low Al composition range. Transistor channel temperatures determined using micro-Raman thermography were consistent with 3-D finite element thermal simulation using the measured thermal conductivities. Changing from a GaN buffer to Al_0.01Ga_0.99N gives rise to a 46% increase in the overall thermal resistance. Increasing Al composition to x = 0.06 increased thermal resistance by a further 35% beyond that of x = 0.01. This result highlights the importance of considering the electrothermal trade-off when tuning Al composition in the lower range to optimize electrical performance, while minimizing the impact on the transistor thermal resistance.