Abstract
The thermal characteristics of large area GaN HEMTs on 200 mm QST engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST substrates are extracted through Raman thermography combined with 3-D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST is up ~1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.
Funding Information
  • Royal Academy of Engineering through the Chair in Emerging Technologies Scheme (EP/Z531091)
  • Innovation and Knowledge Centre REWIRE funded by the Engineering and Physical Sciences Research Council (EP/Z531091)

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