Eric Beyne

Nowadays the AI\HPC devices are becoming more advanced, therefore, the demand for larger packages is rising. However, increased package sizes are causing larger warpage levels to occur. As a result of larger warpage levels, the effects of warpage on the thermal performance of Thermal Interface Materials (TIMs) inside the packages become more critical. However, current thermal characterization methodologies (e.g., ASTM D5470) use ideal surface conditions during testing and overlook the effects of chip package interactions, such as temperature and pressure dependent warpage during operation. Such conditions could deteriorate the contact or coverage of TIMs with die and the heat spreader/heat sink elements in the package. In addition, lack of fully coupled thermal and mechanical analysis of TIMs inside IC packages increases the risk of selecting improper TIMs, which might cause thermal performance issues. To address these problems, we combine in-situ thermal characterization of TIMs using packaged thermal test vehicles and fully coupled thermal and mechanical modelling of the package in realistic application conditions. Fully coupled thermal and mechanical modelling includes the assembly induced warpage, warpage induced gaps at TIM-Cold Plate interface, pressure dependent TIM coverage and their overall effects on the thermal performance of both TIM and the packaging. The results of this study show that warpage of the die can play a crucial role in the thermal performance of the package based on the mechanical properties of the thermal interface materials, bond line thickness and pressure. Using the coupled thermal and mechanical modelling, the mechanisms behind the non-uniform temperature distributions measured by packaged thermal test vehicle are explained, as the temperature difference between the center and the corner of the chip can increase up to a factor 2, caused by warpage induced gaps. Outcomes of this work can be used as a guideline for selecting proper thermal interface materials for improved thermal management of IC packaging.

This paper explores the challenges of microbump pitch scaling down to 5 μm for chiplet applications, including TCB tool alignment accuracy, fabrication process limitations, CTE mismatch, metal oxide reduction, and reliability concerns for die to wafer bonding. An approach called embedded bumps together with fluxless TCB are introduced to mitigate the challenges. Additionally, it discusses qubit, interposer and CMOS chips integration in 2.5D chiplet and 3D architectures for cold and quantum computing applications, where indium is used as the solder metal where successful bonding results for 20 μm pitch indium bumps are shown.

Accurate modeling of on-chip passive components is vital for reliable integrated circuit (IC) design. However, this is non-trivial due to the inherent heterogeneity of the structures and the wide range of material parameters involved. In this work, we present a single-source boundary integral equation (BIE) for modeling on-chip interconnects and passive elements. To reduce the number of discretization elements—and thus the number of unknowns—we construct a 3-D differential surface admittance (DSA) operator for piecewise homogeneous cuboidal and rectilinear polyhedral objects. Specifically, a novel method is proposed to handle material interfaces efficiently. By combining this new formulation of the DSA operator with the augmented electric field integral equation (EFIE), we obtain a framework that enables accurate modeling and fast broadband impedance extraction of on-chip structures. The proposed approach is validated through several numerical experiments, including important applications such as metal-insulator-metal (MIM) capacitors, and demonstrates excellent agreement with reference solutions while significantly reducing computational cost compared to state-of-the-art solvers.

The increasing demand for higher functional density in microelectronics necessitates the miniaturization of interconnects in 3D integration, which presents challenges in processing and reliability. During fabrication and service life, interconnect microbumps remain in a non-equilibrium state, leading to interfacial reactions and atomic diffusion that drive intermetallic compounds (IMCs) growth and phase transformations, impacting the electrical, thermal, and mechanical properties, and affecting long-term reliability. With global restrictions on Pb-based solders, indium (In) has emerged as a viable low-melting-point alternative, especially for temperature-sensitive packaging. Understanding IMCs kinetics in In-based systems is essential for optimizing reliability. This study investigates the kinetics and phase transformation of IMCs in Ni/In and Cu/In systems under solid-state aging conditions using an in-situ resistance measurement technique. The approach overcomes the limitations of traditional scanning electron microscopy (SEM)-based analysis by enabling continuous monitoring of IMCs growth. The Ni/In system forms Ni₃In₇ through a reaction-controlled mechanism with an activation energy of 108 ± 30 kJ/mol. In the Cu/In system, CuIn₂ is formed at room temperature that undergoes a phase transformation to Cu₁₁In₉ via a peritectoid reaction above 107.5 °C of iso-thermal aging. The transformation shifts from a reaction-diffusion mixed controlled regime at 110 °C (n ≈ 0.73) to diffusion control between 120-140 °C (n ≈ 0.45–0.62), and possibly to grain-boundary diffusion at 150 °C (n ≈ 0.19). The activation energy for CuIn₂ → Cu₁₁In₉ transformation is 196 ± 82 kJ/mol, indicating a higher energy barrier. These findings contribute to the development of low-temperature bonding techniques and fine-pitch interconnect optimization for future microelectronics packaging.

Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si $_{\text{0.75}}$ Ge $_{\text{0.25}}$ etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.

As high-power electronics cooling for high heat fluxes above 100 W/cm ² continues to become a more and more pressing matter, work to provide an efficient and effective cooling solution in turn continues also. In the ecosystem of active liquid cooling solutions, it is the cooling performance that is provided within a given flow rate and pressure drop budget that determines efficiency. Liquid jet impingement on the bare die has been proven to provide good cooling performance that is not impeded by the thermal resistance of thermal interface materials. However, system optimizations are also necessary to provide the desired cooling performance within the restrictions of flow rate and pressure drop. A modeling study and experimental demonstrations were done in this work to showcase improvement options within restricted operating conditions. The modeling study shows that adjustment of inlet- and outlet-nozzle diameter, nozzle-to-target spacing, and nozzle pitch allows for optimizing the achieved heat transfer coefficient at given operating conditions. Based on this modeling study, a reference cooler and different improved demonstrators were built and within the same budget for coolant flow rate and driving pressure drop an improvement of effective heat transfer coefficient by 122% from 4.9 W/cm ² K to 10.4 W/cm ² K was achieved.

With ever increasing integration density of electronic components, the demand for cooling solutions capable of removing the heat generated by such systems grows along with it. It has been shown that a viable answer to this demand is the use of direct liquid jet impingement. While this method can generally be scaled to the cooling of large areas, this is restricted by the necessity of coolant flow rate scaling. In this study, the benefits and restrictions of using increased nozzle pitch to remedy the increasing demand for overall flow rate are investigated. To this end, a model is validated against experimental findings and then used for computational fluid dynamics simulations, exploring effects of the pitch change for micro-scale nozzle diameters and nozzle-to-target spacings. It is found that while this method is efficient in adjusting the tradeoff between total coolant flow rate and pressure drop up to a certain pint, the occurrence of a hydraulic jump in the cavity causes a deterioration of its effect for large nozzle pitches.

Customer need for faster electronic products, with enhanced functionalities and smaller form factor is driving the growth of the microelectronic industry. As the traditional more Moore approach is slowing down due to the exponential cost of silicon scaling and the lowers yields [1], a chiplet-based future is being adopted [2, 3]. Chiplets enable modular products by combining chips from various technologies and technology nodes, allowing designs out of reach of the monolithic approach [4, 5]. To tackle the inherent interconnect latency observed in the 2.5D-System-on-Chip (SoC) approach, 3D interconnects technologies are a must. Nevertheless, to enable advanced 3D-SoC circuits, the 3D interconnect pitch needs to be scaled further. This can be achieved using Through Silicon Vias (TSV) [6-8] and wafer-to-wafer (W2W) hybrid bonding [9, 10], in combination with nano-TSVs connecting back-side buried power rails [11]. While TSVs are used to electrically connect the front side to the back side of a silicon wafer, and thus to enable die stacking, W2W hybrid bonding connects directly two wafers through copper pads embedded in a dielectric material which is generally SiO₂ [12, 13] or SiCN [14]. Unfortunately, these novel technologies come along with key reliability issues. TSV’s aggressive aspect ratios (up to 20:1 [15]) put stringent requirements on the etch and liner deposition process to guarantee the electrical isolation and avoid copper diffusion in the silicon substrate [16]. Additionally, their sole presence has been shown to influence the reliability of the above BEOL layers [17, 18] and near-by transistors [6]. In the hybrid-bonding technologies, the constant pitch down-scaling results in an increased leakage current along the bonding interface [19] which can be further enhanced by pad-to-pad misalignment [20]. While this misalignment can be mitigated with unequal pad schemes [21], the resulting copper-dielectric interface could lead to metal ion drift at elevated temperature and electric fields [19]. In this presentation, the reliability issues and failure mechanisms linked to 3D technologies will be discussed and a particular focus will be given on topics which are currently of interest at imec. The controlled-IV methodology, used to assess dielectric material reliability will be reintroduced. Data obtained on 1 x 5 µm TSVs will demonstrate the advantage of imec embedded barrier to mitigate reliability issues arising from copper resputtering during the etch process while the importance of an optimized etch recipe will be shown. Reliability characterizations of SiCN-based hybrid bonded structures, down to a pitch of 700 nm will be presented along with a discussion on the influence of the CMP process on the leakage current and resulting lifetime. The potential influence of copper ion diffusion along the bonding interface will be analyzed. Finally, the impact of electromigration on the copper pads will be presented. [1] Samavedam, S. B. et al., IEDM, 2020. [2] Cao, L., IEDM, 2022. [3] Beyne, E. et al., IEDM, 2021. [4] Su, L. et al., IEDM, 2017 [5] Naffziger, S.et al., IEEE ISSCC, 2020. [6] Croes, K., et al., IEEE Design & Test , 2016, Vol. 33, No. 3. [7] Burkett, S. et al., Journal of Vacuum Science & Technology A, 2020, Vol. 38, No. 3. [8] Van Huylenbroeck, S. et al., ECTC, 2019. [9] Jouve, A. et al., SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017. [10] Kim, S-W. et al., ECTC, 2020. [11] Jourdain, A. et al., ECTC, 2022. [12] Utsumi, J., et al., Micro and Nano Engineering, 2019, Vol. 2 [13] Ayoub, B et al., EPTC, 2020. [14] Iacovo, S. et al., ECTC, 2022. [15] Van Huylenbroeck, S et al., IEEE 3DIC, 2016 [16] Li, Y. et al., Microelectronics Reliability, 2013, Vol. 54, No. 9-10 [17] Frank, T. et al., Microelectronics Reliability, 2013, Vol. 53, No. 1 [18] Li, Y. et al., IRPS, 2014. [19] Hou, Lin et al., IRPS, 2022. [20] Ayoub, B. et al., IRPS, 2022. [21] Kim, S-W., et al., ECTC, 2020.