Ingrid De Wolf

We apply our finite element-based framework, introduced in Part 1, to understand the effects of channel thickness and doping on the degradation of indium–gallium–zinc oxide (IGZO)-based thin-film transistors (TFTs) with different architectures. By taking into account only experimentally extracted band alignments and amorphous semiconductor-specific physics, it is possible to explain apparent discrepancies in previously reported positive bias temperature instabilities (PBTI) trends. Our analysis shows that common PBTI benchmarks used in standard inversion-mode bulk Si devices cannot be employed in thin-film accumulation-mode IGZO devices. Finally, based on these insights, we propose device optimization strategies to reduce the electron trapping component of PBTI in amorphous IGZO TFTs.

We present a finite-element-based 1-D formalism to solve the Poisson equation for a thin-film transistor with a floating body. We apply our framework to InGaZnO (IGZO)-based devices, taking into account its subgap density of states (DoS), revealing its impact on device electrostatics, which is fundamental for predicting device performance and reliability. Our simple 1-D approach yields identical results as the more computationally intensive 2-D TCAD implementations, and it enables the convenient implementation of physics-based IGZO-specific models. Finally, we apply the new framework to quantify the IGZO deep subgap DoS measured by light-assisted $I$ – $V$ spectroscopy.

Infrared (IR) thermal imaging at ambient temperature using conventional IR cameras often faces challenges such as reduced image contrast and elevated noise levels, restricting its application in high-resolution microscopic imaging. In this Letter, we report an in-situ lock-in infrared illumination approach to enhance the IR image quality. By combining mid-wave IR (MWIR) illumination with lock-in synchronization, the proposed method improves image contrast, enhances resolving capability, and suppresses noise in the image effectively, important for microscopic thermal imaging. The method is validated through the demonstration of defect localization in GaAs nano-ridge lasers, highlighting its practical application. This in-situ non-contact approach offers several advantages over the contrast enhancement methods reported in the literature and can be readily integrated into existing thermal imaging systems.

The combined effect of thermomigration (TM) and electromigration (EM) on the reliability of Cu interconnects is investigated. Package-level EM+TM tests were conducted to understand the impact of temperature gradients on void nucleation and void growth in the presence of electrical currents. Through failure analysis, void nucleation at the via bottom followed by subsequent void growth toward adjacent vias is confirmed. An analytical model is developed to quantify the impact of temperature gradients on EM lifetime. Results indicate that thermal gradients have a more pronounced impact at lower ambient temperatures, reducing EM lifetime by approximately 50% at 100 ∘C, compared to a 42% reduction at 300 ∘C. This work enhances the understanding of EM+TM coupling mechanisms and provides a practical model for predicting

In this work, we investigate 10-keV X-ray-induced TID effects in VPIN photodiodes using calibrated TCAD simulations. We demonstrate that positive trapped charges near the space-charge region locally increase the electric field magnitude, enhancing Shockley–Read–Hall (SRH) generation-recombination and trap-assisted tunneling (TAT) rates, thereby impacting dark current, forward current, and the ideality factor. Simulations indicate that charge trapping at the top-corner Ge/SiO₂ interfaces accurately reproduces experimental trends. In contrast, photocurrent and junction capacitance remain largely unaffected, attributed to the large area-to-perimeter ratio of the device, which reduces the influence of localized interface degradation.

We report forward bias and temperature-dependent low-frequency (LF) noise characteristics of waveguide-integrated Ge-on-Si p–i–n photodiodes across three architectures: doped-Si lateral, doped-Ge and doped-Si lateral, and vertical heterojunctions. Forward I–V measurements and activation energy analysis reveal mixed Shockley–Read–Hall recombination and diffusion transport below 0.4 V, with transport ratios evolving more gradually with temperature in vertical devices than in lateral devices. At room temperature, the noise spectra exhibit broad generation-recombination (G–R) features near V=0.2 V, aligning with the transition from G–R-dominated (SI∼I2 for V≤0.2 V) to diffusion-limited (SI∼I for 0.2V≤V≤0.5V) current noise. Technology computer-aided design simulations indicate that in lateral devices the defect-rich Ge/Si interface lies within the depletion region, where interface traps strongly enhance G–R noise. In vertical devices, the Ge/Si interface is located outside the depletion zone, so the noise response is dominated by bulk Ge traps. Temperature-dependent measurements reveal a smooth transition from G–R noise below 300 K to diffusion-type flicker noise at higher temperatures. Notably, normalized noise SI/I2 peaks around 300 K in lateral devices, marking a crossover in dominant noise mechanisms. Observed increases of low-temperature noise after total-ionizing-dose irradiation in lateral devices result from the electrostatic activation of traps within the narrow depletion region, whereas the increase of forward current originates mainly from radiation-induced additional leakage paths. These results establish LF noise spectroscopy as an effective tool for probing interfacial defect dynamics in Ge-on-Si photodiodes.

The increasing demand for higher functional density in microelectronics necessitates the miniaturization of interconnects in 3D integration, which presents challenges in processing and reliability. During fabrication and service life, interconnect microbumps remain in a non-equilibrium state, leading to interfacial reactions and atomic diffusion that drive intermetallic compounds (IMCs) growth and phase transformations, impacting the electrical, thermal, and mechanical properties, and affecting long-term reliability. With global restrictions on Pb-based solders, indium (In) has emerged as a viable low-melting-point alternative, especially for temperature-sensitive packaging. Understanding IMCs kinetics in In-based systems is essential for optimizing reliability. This study investigates the kinetics and phase transformation of IMCs in Ni/In and Cu/In systems under solid-state aging conditions using an in-situ resistance measurement technique. The approach overcomes the limitations of traditional scanning electron microscopy (SEM)-based analysis by enabling continuous monitoring of IMCs growth. The Ni/In system forms Ni₃In₇ through a reaction-controlled mechanism with an activation energy of 108 ± 30 kJ/mol. In the Cu/In system, CuIn₂ is formed at room temperature that undergoes a phase transformation to Cu₁₁In₉ via a peritectoid reaction above 107.5 °C of iso-thermal aging. The transformation shifts from a reaction-diffusion mixed controlled regime at 110 °C (n ≈ 0.73) to diffusion control between 120-140 °C (n ≈ 0.45–0.62), and possibly to grain-boundary diffusion at 150 °C (n ≈ 0.19). The activation energy for CuIn₂ → Cu₁₁In₉ transformation is 196 ± 82 kJ/mol, indicating a higher energy barrier. These findings contribute to the development of low-temperature bonding techniques and fine-pitch interconnect optimization for future microelectronics packaging.

In this work, an in-depth study of the strain originating from the metallic pads of field effect transistors with WS₂ channels are reported. Presence of tensile strain caused by Ni/Pd pads fabricated with a lift-off process is confirmed with high resolution tip-enhanced Raman and photoluminescence. This strain field appears to extend in the 1–2 µm vicinity of the pads and affect the optical bandgap of the layer. The severity and the profile of the mechanical stress seems to depend on factors like device architecture, channel length, and the contact area of the pads. Results indicate that the optical response of the channel can be correlated to the field-effect mobility, both factors reflecting the quality of the crystal, and be utilized in robust assessment of mechanical stress in these devices.

In this paper, we introduce a modular thermal modeling methodology, BTE-FEM, that combines the Boltzmann Transport Equation (BTE) with Finite Element Modeling (FEM) for simulations of advanced back-end-of-line (BEOL) stacks with high accuracy and efficiency. BTE-FEM is validated against direct BTE-based simulations using simplified BEOL stack test cases across various technology nodes and via connectivity configurations. It is demonstrated that conventional FEM, using bulk material properties, increasingly underestimates the BEOL thermal resistance as the technology node scales. In contrast, the BTE-FEM developed in this study demonstrates good agreement with direct BTE simulations for all test cases, but at much shorter runtimes. The impact of material properties, metal densities, and boundary conditions on the derived BEOL thermal properties are benchmarked and the developed models are experimentally validated at two distinct technology nodes. Finally, the developed methodology is applied to a 12-layer, 18 nm metal pitch BEOL stack from an A10 high density core design, demonstrating its ability to simulate complex and realistic BEOL routings with the precision of direct BTE simulations while substantially reduced simulation time. This approach enables extensive Design of Experiments (DOE) for fast turnaround design iterations.

A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.