Manuel J. Barragan

This article presents an innovative electrostatic discharge (ESD) protection concept based on the integration of gated diodes within metal–oxide–metal (MOM) capacitors, targeting RF applications in advanced CMOS technologies. The proposed ESD capacitor maintains a high quality factor ( $Q$ ) while providing robust protection against fast transient events, such as those qualified by the charged device model (CDM). The design leverages miniaturized gated diodes and a codesign approach to preserve RF performance without area overhead. Characterization results, including transmission line pulse (TLP), very fast TLP (VF-TLP), and capacitively coupled TLP (CC-TLP) tests, demonstrate superior robustness compared to unprotected circuits, with failure currents exceeding 15.1 A in simulations and above 13 A in measurements. The integration of the ESD capacitor into a low-noise amplifier (LNA) operating in the 6–12 GHz range confirms minimal impact on RF parameters such as gain, noise figure, and input matching. These results validate the effectiveness of the proposed solution for high-frequency ESD protection in scaled CMOS technologies.

This work proposes the use of machine learning-based techniques for enhanced testability and performance calibration of an industrial 79-GHz power amplifier (PA) designed for an automotive radar system. The proposed techniques are based on a set of built-in test structures including nonintrusive process monitors based on digital ring oscillators and a built-in reflectometer. The indirect signatures provided by these test structures allow us to do the following: 1) identify defective instances of the PA under test; 2) evaluate the quality of the output matching adaptation; and 3) calibrate the performance of the PA to compensate for process variations. Defect detection is based on a defect filtering algorithm that employs outlier identification techniques; mismatch evaluation employs a machine learning regressor; and, finally, the proposed performance calibration is based on a one-shot statistical calibration that predicts the optimum configuration of the PA. The proposed techniques are experimentally demonstrated on a set of 32 fabricated chips designed in 28 nm CMOS technology.

This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately describing the behavior of the transistor DC drain current in all regions (linear to saturation) and regimes of operation (weak to strong inversion). The proposed model is critically compared to existing inversion charge-based models, highlighting the main limitations of previous models presented in the literature and the advantages and disadvantages of our proposal. Then, regarding the model implementation, previously presented inversion charge-based models require a numerical solver to link the transistor’s DC current to its DC node voltages. In this work, we propose an innovative approach to model implementation via the analytical approximation of the Lambert function’s principal branch. Thanks to this approximation, the proposed design-oriented model offers for the first time an analytical single-piece expression of the drain current as an explicit function of the transistor node voltages. The validity of both the proposed transistor DC model and its analytical single-piece implementation is confirmed through simulation and measurement results, using the industrial productionlevel model UTSOI2 as a reference. The evaluations were conducted on MOS transistors with lengths of 30 nm, 60 nm, and 150 nm in STMicroelectronics 28 nm FD-SOI CMOS technology, to validate our results in minimum length, intermediate length, and long transistors in the selected technology. The proposed model achieves an average error of less than 6% in drain current evaluation compared to industry-standard models such as UTSOI2, while significantly reducing computational complexity.

This article proposes a general approach to accurately model the N-path filters and mixers, with the double purpose of bringing a better insight in the frequency transposition phenomena and opening the door towards a more general discussion concerning NPF-NPM and their outstanding properties as passive circuits. Thanks to a Fourier transform analysis, some mathematical equations are rigorously derived for both filtering and mixing voltage gains. The analysis is compared with ideal simulations for various sets of parameters: source impedance $R_a$ , load impedance $R_L$ , switch resistance $R_{sw}$ , capacitive path $C_L$ . Some error curves are extracted validating the initial hypotheses for the model in a given range of capacitances values. As a proof of concept, it is shown that the model complies with the measurements results with very good accuracy. The error is less than 10.5 $\%$ on the two first harmonics prediction.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the $7^{th}$ local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the $3^{rd}$ , $5^{th}$ , and $7^{th}$ LO harmonics, 13 dB gain, 13.3 dB NF, $-$ 3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of 0.62 $\times$ 0.22 $mm^{2}$ .

This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4 GHz low-noise-amplifier in a 28 nm FD-SOI CMOS technology. Obtained results in terms of S ₁₁ , S ₂₁ , NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

State-of-the-art nanometric fabrication processes enable the integration of monolithic millimeter-wave (mm-wave) circuits. However, nanometric technologies are prone to process variations that may significantly impact the performance of the fabricated mm-wave circuits and dramatically reduce the fabrication yield. In order to improve the fabrication yield, extensive resources are required for tuning the functionality of each fabricated die in the production line, especially in the mm-wave domain. In this work, we implement and experimentally validate a machine learning-based calibration strategy for mm-wave circuits that significantly simplifies this tuning process. A machine learning algorithm is employed to predict the optimum values of a set of on-chip tuning knobs based on nonintrusive measurements provided by embedded process monitor circuits. The proposed technique is demonstrated on a 69-GHz power amplifier (PA) with one-shot calibration capabilities integrated in STMicroelectronics 55-nm CMOS technology. The experimental results on a set of 39 fabricated samples demonstrate the feasibility and performance of the proposed machine learning-based calibration for yield recovery and performance recentering applications.

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