Loic Vincent

This work proposes the use of machine learning-based techniques for enhanced testability and performance calibration of an industrial 79-GHz power amplifier (PA) designed for an automotive radar system. The proposed techniques are based on a set of built-in test structures including nonintrusive process monitors based on digital ring oscillators and a built-in reflectometer. The indirect signatures provided by these test structures allow us to do the following: 1) identify defective instances of the PA under test; 2) evaluate the quality of the output matching adaptation; and 3) calibrate the performance of the PA to compensate for process variations. Defect detection is based on a defect filtering algorithm that employs outlier identification techniques; mismatch evaluation employs a machine learning regressor; and, finally, the proposed performance calibration is based on a one-shot statistical calibration that predicts the optimum configuration of the PA. The proposed techniques are experimentally demonstrated on a set of 32 fabricated chips designed in 28 nm CMOS technology.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the $7^{th}$ local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the $3^{rd}$ , $5^{th}$ , and $7^{th}$ LO harmonics, 13 dB gain, 13.3 dB NF, $-$ 3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of 0.62 $\times$ 0.22 $mm^{2}$ .

A 76–81-GHz dual-path receiver in 28-nm FD-SOI CMOS technology is presented for automotive radar applications. It introduces a new accurate phase control of phased-array radars using MOS varactors. The proposed solution is analytically described and implemented in the front-end low-noise amplifier (LNA) of each receiver path. It allows a maximum phase control of 23 $^{\circ}$ with less than a 1 $^{\circ}$ resolution for minimum degradation of the receiver performances. The receiver contains a two-stage LNA, a passive mixer, a local oscillator (LO) driver, and a baseband amplifier (BBA). The receiver achieves a 6.2 dB noise figure (NF) at 81 GHz. The receiver exhibits input compression points (ICPs $_{\text{1\,dB}}$ ) of $-$ 29.5 and $-$ 14.2 dBm with and without BBA, respectively. The active area of a single receiver path is only 0.057 mm $^{2}$ for a 46.1 mW power consumption and the active area of the dual-path receiver is 0.28 mm $^{2}$ .

State-of-the-art nanometric fabrication processes enable the integration of monolithic millimeter-wave (mm-wave) circuits. However, nanometric technologies are prone to process variations that may significantly impact the performance of the fabricated mm-wave circuits and dramatically reduce the fabrication yield. In order to improve the fabrication yield, extensive resources are required for tuning the functionality of each fabricated die in the production line, especially in the mm-wave domain. In this work, we implement and experimentally validate a machine learning-based calibration strategy for mm-wave circuits that significantly simplifies this tuning process. A machine learning algorithm is employed to predict the optimum values of a set of on-chip tuning knobs based on nonintrusive measurements provided by embedded process monitor circuits. The proposed technique is demonstrated on a 69-GHz power amplifier (PA) with one-shot calibration capabilities integrated in STMicroelectronics 55-nm CMOS technology. The experimental results on a set of 39 fabricated samples demonstrate the feasibility and performance of the proposed machine learning-based calibration for yield recovery and performance recentering applications.

This article presents a matrix-based model suitable for millimeter-wave (mm-wave) distributed amplifier (DA) design, based on four-port chain (ABCD) formalism. Using this model, an algorithmic design methodology for DA, built upon a loss-compensation technique, is also provided that maximizes its bandwidth (BW) for a given flatness goal. The design approach provides fast and accurate design space exploration (DSE) plots that enable one to examine the tradeoffs between gain, BW, power consumption ( $\mathrm {P}_{\mathrm {DC}}$ ), and the size and number of Gm-cells, and arrive at the optimum desired design. Its benefit is demonstrated by means of a computer-automated design (CAutoD) example where 55-nm CMOS STMicroelectronics (ST) process is used and DAs with BWs $\ge80$ GHz were desired to be sized; reporting 216 feasible DA options to explore from. The global optimum DA amplifying frequencies up to 100 GHz was then implemented as a circuit prototype. The measured DA provided 6.7-dB power gain while requiring a power consumption ( $\mathrm {P}_{\mathrm {DC}}$ ) of 30 mW from a 1.2-V supply. The chip occupied a total area of 0.83 mm2. Compared to state-of-the-art FET-based small-signal DAs, the fabricated circuit reports the highest gain-bandwidth product (GBP) per $\mathrm {P}_{\mathrm {DC}}$ ( ${\mathrm {GBP}} \mathord {\left /{ {\vphantom {{\mathrm {GBP}} \mathrm {P}_{\mathrm {DC}}}} }\right. } \mathrm {P}_{\mathrm {DC}}$ ) of 6.01 GHz/mW while being power-efficient.

The design and experimental results of millimeter-wave bandpass filters (BPFs) implemented in 55-nm BiCMOS technology and operating around 120 GHz are presented in this article. Slightly modified coupled line filters' structures are used in the designs. It allows generating the transmission zero at the upper stopband, leading to the selectivity of enhanced filters. The coupled line structure is implemented in two technologies, microstrip coupled lines and coupled slow-wave (SW) coplanar waveguides (CS-CPWs). The latter shows more design flexibility, allowing to reach a better filtering performance than the microstrip filters, i.e., better in-band flatness and higher selectivity. Good agreement is achieved between simulation, modeling, and measurement results. Also, the overall length of the filter based on CS-CPWs is smaller as compared to the filters based on the microstrip lines, thanks to the SW propagation.

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection.

This article focuses on the design of high-performance coupled slow-wave coplanar waveguide (CS-CPW) in CMOS technologies for the millimeter-wave (mm-wave) frequency bands. First, the theory as well as the electrical model of the CS-CPW are presented. Next, the analytical approach for the calculation of the model parameters is discussed. Then, by using the developed model, two mm-wave backward directional 3-dB couplers are designed in a bipolar complementary metal-oxide-semiconductor (BiCMOS) 55-nm technology for 120- and 185-GHz operation, respectively. Simulation and experimental results demonstrate that the use of the CS-CPW concept leads to state-of-the-art performance, with a good agreement between the analytical model, electromagnetic simulations, and measurement results.