Leo Raj Solay

In this work, enhancement-mode p-MOSFETs on p-GaN/AlGaN/GaN-on-Si substrates were fabricated using a gate recess process that combines reactive ion etching (RIE) with atomic layer etching (ALE), where ALE is employed as an interface engineering approach following conventional plasma etching to mitigate recess-induced interface damage. Compared with RIE-only devices, the RIE + ALE devices yield smoother surfaces and significantly suppress interface trap density. These interface improvements lead to enhanced subthreshold characteristics and markedly tighter device-to-device uniformity. In particular, the subthreshold swing decreased from 365 ± 179 to 149 ± 17 mV/dec, while the off-state leakage current was suppressed from 1.9 ± 3.6 × 10−7 to 8.5 ± 5.5 × 10−9 mA/mm. These results demonstrate that ALE provides an effective interface engineering approach for suppressing interface damage and enabling uniform enhancement-mode p-MOSFETs, highlighting its potential for reliable GaN complementary metal–oxide–semiconductor logic and power integrated circuits.

Reliable engineering of low-resistance metal semiconductor (M/S) contacts is critical for advancing indium oxide (In2O3) based semiconductor technologies. As device dimensions shrink to the micrometer regime, minimizing contact resistance becomes essential to ensure channel limited operation rather than contact dominated. In this study, we systematically optimized Ni/In2O3 contacts using mild rapid thermal annealing (RTA) at 250 °C in nitrogen ambient conditions compatible with back-end-of-line (BEOL) processing and evaluated their performance using the transfer line method (TLM). Ni/In2O3 TLM structures were fabricated via photolithography and liftoff, followed by RTA at varying durations. Quantitative TLM analysis demonstrated a substantial reduction in contact resistance (RC) to 6.24 Ω, normalized contact resistance (N · RC) to 1.25×10−1 Ω cm, specific contact resistivity (ρC) to 1.53×10−6 Ω cm2, and a short transfer length (LT) of 123 nm, all achieved without intentional doping or complex metallization. This process driven, BEOL compatible approach provides a robust route to low-resistance contacts in In2O3 thin films, enabling a reliable foundation for next generation low power, high performance oxide electronics.

The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In ₂ O ₃ ) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V ⁻¹ and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions.

This paper proposes a highly sensitive nanoscale label-free biosensor upon charge plasma based gate-all-around nanowire dopingless field effect transistor (GAA NW DL FET Biosensor) for the detection of biomolecules. The proposed sensor device structure employs charge plasma and dopingless approaches to eliminate the requirement for doping. The thermionic emission of FET structures increases the device’s current sensitivity (S_I) for various targeted biomolecules introduced through the nanocavity created at the source side/metal of the proposed biosensor. To test the significant sensing performance of the device proposed herein, the biomolecules streptavidin with a dielectric constant (K) of 2.1, 3-aminopropyltriethoxysilane (APTES) with a K value of 3.57, and protein with a K value of 8 are utilized. The proposed sensor resulted in drain current sensitivity as high as 1.4 of protein biomolecule. An extensive analysis was performed to evaluate the efficiency of the proposed sensor with process-related issues such as cavity length variations ranging from 21 nm to 3 nm and real-time related issues such as fill factor variations ranging from 20% to 100% and interface charges for the targeted biomolecules, and their sensitivity parameters were investigated, demonstrating the promising features of GAA NW DL FET biosensor as an ultrasensitive biosensor for clinical applications.

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

In this work, the impact of negative capacitance upon Charge plasma Junctionless Nanowire Tunnel Field Effect Transistor (NC JL NWTFET) is proposed and investigated. A dopant free technique charge plasma is applied to the proposed device which excludes the need for doping for the creation of source and drain terminals which reduces the Random Dopant Fluctuations (RDFs) and Expensive Thermal Budget (ETB). The channel length of 20nm and radius of 7.5nm is used for designing the proposed device. Simulations using Silvaco TCAD coupled with Landau Khalatnikov (LK) coefficients of ferroelectric are used. The negative capacitance approach enhances the non-hysteric operation which can ultimately be used for minimal power purposes. To analyze the ideal required bias, LK equations are used for determining the ferroelectric thickness and to calculate the impact of NC, the ferroelectric PZT having perovskite properties is used near gate as an insulator. The thickness of ferroelectric is the major factor as it can lead to hysteresis So, the thickness needs to be carefully selected. The investigation is done with the comparison of with NC and without NC upon JL NWTFET. With the negative capacitance approach the proposed device exhibited I ON of 1.17 (μA) at reduced operating voltage of 0.5V. Device comparison with respect to analog and linearity analysis is demonstrated proving the device capability for low power applications.

In this paper, a novel low power consumption device based on a dopingless gate-all-around nanowire tunnel field effect transistor (TFET) with negative capacitance (NC) effect is proposed. NC is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, the threshold voltage ( V _T ) and subthreshold swing (SS) are dropped significantly to less than 60 mV/decade. Negative capacitance makes a significant contribution to the device’s performance by lowering the operating voltage for low-power applications. To calculate the optimum bias, the Landau–Khalatnikov (L–K) equation was used. To evaluate the influence of NC, the ferroelectric (FE) material PZT (lead zirconate titanate), which has perovskite properties, was used as a gate insulator. Thus, the gate-all-around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA NC DL NW TFET. PZT has an appropriate polarization rate, high dielectric capacitance, and a high degree of reliability. To achieve an SS lower than 60 mV/decade at lower V _T , effective tuning of the FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device. The aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of the dopingless technique to the nanowire-based TFET. The enhancement of the ON-current with an improved steep SS was addressed. With the application of the NC technique, the proposed device showcased an improved 4 µ A µ m ⁻¹ of I _ON , and 10 ¹² of current ratio. Additionally, the influence of the variation in FE thickness on the performance parameters is examined. The proposed device structure operates at a minimum operating voltage, making it an ideal choice for low-power voltage applications.

Reported work demonstrates the application of common source amplifier circuit using the proposed Gate Stack based Gate All Around Dopingless Nanowire Field Effect Transistor (GS GAA DL NW—FET) structure. Primarily, impact of the gate stack (GS) technique on the conventional Gate All Around Dopingless Nanowire Field Effect Transistor (GAA DL NW—FET) structure is explored. The proposed FET structure resulted in excellent electrostatic control over the channel by incorporating the advantages of GAA architectures and dopingless technique. As transfer characteristics of conventional GAA DL NW—FET have been enhanced with gate stack (SiO₂ + high k) technique when employed at dielectric region. A contrast is drawn between both structures in terms of analog parametric analysis which resulted in improved I_ON of 30.6 (μA), reduced I_OFF of 10⁻⁷ (μA) and enhanced I_ON/I_OFF of 6.7 × 10⁷. Linearity analysis were made to examine the distortion less digital communication and a fair comparison is depicted between the structures. CS amplifier circuit application with proposed GS GAA DL NW—FET resulted in improved V_OUT with 15.2 dB of gain when compared with GAA DL NW—FET based CS amplifier which stood at 13.9 dB which proves the promising candidature for forthcoming nanoscale circuit applications.

The reported work demonstrates the application of common source amplifier circuit using gate-all-around gate stacked charge plasma nanowire field effect transistor (GAA GS CP NW FET). Primarily, the impact of the gate stacking (GS) technique upon the Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA CP NW FET) structure is explored. In which GAA GS CP NW FET structure resulted in excellent electrostatic control over the channel by incorporating the advantages of GAA structures. The transfer characteristics have been enhanced with the gate stacking (SiO₂ + high k) technique when employed at the dielectric region of the structure. The charge plasma concept which is applied in the proposed device helped in reducing the threshold voltage fluctuations. A contrast is drawn between GAA CP NW FET and GAA GS CP NW FET structures in terms of analog and RF analysis. Linearity parametric analysis were made to examine the distortion less digital communication and a comparison is made between the structures. The proposed structure is then utilized for designing a common source amplifier circuit and contrasted with the GAA CP NW FET structure. With the applied gate stacking technique, the proposed structure resulted in improved ON-current, reduced OFF-current, enhanced current ratio. The CS amplifier circuit application resulted in improved V_out and gain attributes with the proposed GAA GS CP NW FET structure when compared with Metal Oxide Semiconductor FET (MOSFET), Tunnel FET (TFET) and GAA CP NW FET structure proving its capability for forthcoming nanoscale circuit applications.